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Searched refs:CACHE64_CTRL_CLCR_LGO_MASK (Results 1 – 25 of 38) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h991 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
997 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMIMXRT685S_cm33.h6299 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
6305 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6299 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
6305 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1347 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
1353 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMIMXRT595S_cm33.h7495 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
7501 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2801 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
2807 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2801 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
2807 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7491 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
7497 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7494 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
7500 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2800 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
2806 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8070 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8076 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMCXN546_cm33_core1.h8070 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8076 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8070 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8076 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMCXN547_cm33_core1.h8070 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8076 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16701 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16707 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMIMXRT798S_cm33_core0.h16744 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16750 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMIMXRT798S_ezhv.h16283 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16289 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16283 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16289 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMIMXRT735S_cm33_core0.h16744 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16750 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16744 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
16750 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8104 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8110 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMCXN947_cm33_core0.h8104 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8110 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8104 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8110 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
DMCXN946_cm33_core1.h8104 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
8110 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13302 #define CACHE64_CTRL_CLCR_LGO_MASK (0x1U) macro
13308 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LGO_SHIFT)) & CACHE64_CTRL_CLCR_LGO_MASK)

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