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Searched refs:CACHE64_CTRL_CLCR_LADSEL_MASK (Results 1 – 25 of 39) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c263 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_InvalidateCacheByRange()
333 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_CleanCacheByRange()
405 …->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK; in CACHE64_CleanInvalidateCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1045 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
1051 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT685S_cm33.h6353 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
6359 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6353 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
6359 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1410 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
1416 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT595S_cm33.h7558 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7564 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2870 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2876 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2870 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2876 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7554 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7560 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7557 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
7563 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2869 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
2875 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8133 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8139 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMCXN546_cm33_core1.h8133 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8139 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8133 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8139 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMCXN547_cm33_core1.h8133 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8139 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16764 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
16770 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT798S_cm33_core0.h16807 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
16813 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16346 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
16352 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMIMXRT735S_cm33_core0.h16807 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
16813 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16807 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
16813 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8167 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8173 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMCXN947_cm33_core0.h8167 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8173 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8167 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8173 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
DMCXN946_cm33_core1.h8167 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
8173 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13356 #define CACHE64_CTRL_CLCR_LADSEL_MASK (0x4000000U) macro
13362 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LADSEL_SHIFT)) & CACHE64_CTRL_CLCR_LADSEL_MASK)

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