Home
last modified time | relevance | path

Searched refs:CACHE64_CTRL_CLCR_LACC_MASK (Results 1 – 25 of 38) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1053 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
1059 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMIMXRT685S_cm33.h6361 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
6367 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6361 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
6367 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1418 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
1424 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMIMXRT595S_cm33.h7566 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
7572 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2878 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
2884 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h2878 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
2884 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h7562 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
7568 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h7565 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
7571 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h2877 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
2883 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h8141 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8147 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMCXN546_cm33_core1.h8141 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8147 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h8141 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8147 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMCXN547_cm33_core1.h8141 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8147 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi4.h16772 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16778 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMIMXRT798S_cm33_core0.h16815 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16821 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMIMXRT798S_ezhv.h16354 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16360 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_ezhv.h16354 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16360 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMIMXRT735S_cm33_core0.h16815 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16821 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core0.h16815 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
16821 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h8175 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8181 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMCXN947_cm33_core0.h8175 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8181 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h8175 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8181 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
DMCXN946_cm33_core1.h8175 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
8181 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h13364 #define CACHE64_CTRL_CLCR_LACC_MASK (0x8000000U) macro
13370 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CLCR_LACC_SHIFT)) & CACHE64_CTRL_CLCR_LACC_MASK)

12