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Searched refs:CACHE64_CTRL_CCR_INVW1_MASK (Results 1 – 25 of 58) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c217 … base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_InvalidateCache()
225 base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in CACHE64_InvalidateCache()
358 CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_CleanInvalidateCache()
367 CACHE64_CTRL_CCR_INVW1_MASK); in CACHE64_CleanInvalidateCache()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_cm33_core0.c105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
124 CACHE64_CTRL1->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_cm33_core0.c105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
124 CACHE64_CTRL1->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_cm33_core0.c105 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
124 CACHE64_CTRL1->CCR = CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/mimxrt685audevk/
Dmflash_drv.c394 …CACHE64->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MA… in mflash_drv_init_internal()
398 CACHE64->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/rdrw612bga/
Dmflash_drv.c375 …CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR… in mflash_drv_init_internal()
379 CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/frdmrw612/
Dmflash_drv.c369 …CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR… in mflash_drv_init_internal()
373 CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/mimxrt700/
Dmflash_drv.c155 …CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR… in CACHE64_Invalidate()
159 CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in CACHE64_Invalidate()
/hal_nxp-latest/mcux/mcux-sdk/components/internal_flash/octal_flash/RT595/
Dfsl_adapter_flexspi_nor_flash.c309 …CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR… in flexspi_nor_invalid_flexspi_cache()
313 CACHE64_CTRL0->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in flexspi_nor_invalid_flexspi_cache()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_cm33.c118 CACHE64->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
DMIMXRT685S_dsp.h963 #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) macro
969 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
DMIMXRT685S_cm33.h6271 #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) macro
6277 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
Dsystem_MIMXRT633S.c117 CACHE64->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
DMIMXRT633S.h6271 #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) macro
6277 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_cm33.c129 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
DMIMXRT595S_dsp.h1319 #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) macro
1325 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.c128 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.c128 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
Dsystem_RW610.c87 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
Dsystem_RW612.c87 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c71 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
76 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
743 cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2773 #define CACHE64_CTRL_CCR_INVW1_MASK (0x4000000U) macro
2779 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_INVW1_SHIFT)) & CACHE64_CTRL_CCR_INVW1_MASK)

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