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Searched refs:CACHE64_CTRL_CCR_GO_MASK (Results 1 – 25 of 58) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/cache64/
Dfsl_cache.c217 … base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_InvalidateCache()
220 while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_InvalidateCache()
287 …ase->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_CleanCache()
290 while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_CleanCache()
358 CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_CleanInvalidateCache()
361 while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_CleanInvalidateCache()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_cm33_core0.c106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
125 CACHE64_CTRL1->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
126 while ((CACHE64_CTRL1->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_cm33_core0.c106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
125 CACHE64_CTRL1->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
126 while ((CACHE64_CTRL1->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_cm33_core0.c106 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
107 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
125 CACHE64_CTRL1->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
126 while ((CACHE64_CTRL1->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
Dsystem_MIMXRT685S_cm33.c119 CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
121 while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
DMIMXRT685S_dsp.h979 #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) macro
985 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
DMIMXRT685S_cm33.h6287 #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) macro
6293 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
Dsystem_MIMXRT633S.c118 CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
120 while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
DMIMXRT633S.h6287 #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) macro
6293 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_cm33.c130 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
132 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
DMIMXRT595S_dsp.h1335 #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) macro
1341 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.c129 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
131 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.c129 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
131 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
Dsystem_RW610.c88 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
90 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
Dsystem_RW612.c88 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in SystemInit()
90 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in SystemInit()
/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.c71 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
72 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
84 …che->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
85 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/mimxrt685audevk/
Dmflash_drv.c394 …CHE64->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in mflash_drv_init_internal()
395 while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/rdrw612bga/
Dmflash_drv.c375 …CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in mflash_drv_init_internal()
376 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/frdmrw612/
Dmflash_drv.c369 …CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in mflash_drv_init_internal()
370 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) in mflash_drv_init_internal()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
751 …che->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
751 …che->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_power.c738 …cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
739 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
751 …che->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in AT_QUICKACCESS_SECTION_CODE()
752 while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-latest/mcux/mcux-sdk/components/flash/mflash/mimxrt700/
Dmflash_drv.c155 …CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in CACHE64_Invalidate()
156 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) in CACHE64_Invalidate()
/hal_nxp-latest/mcux/mcux-sdk/components/internal_flash/octal_flash/RT595/
Dfsl_adapter_flexspi_nor_flash.c309 …CTRL0->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK; in flexspi_nor_invalid_flexspi_cache()
310 while (0 != (CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK)) in flexspi_nor_invalid_flexspi_cache()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h2789 #define CACHE64_CTRL_CCR_GO_MASK (0x80000000U) macro
2795 … (((uint32_t)(((uint32_t)(x)) << CACHE64_CTRL_CCR_GO_SHIFT)) & CACHE64_CTRL_CCR_GO_MASK)

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