| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/ |
| D | core_common.h | 43 #ifndef BIT
44 #define BIT(n) (1 << (n)) macro
48 #define DAIF_F_BIT BIT(6)
49 #define DAIF_I_BIT BIT(7)
50 #define DAIF_A_BIT BIT(8)
51 #define DAIF_D_BIT BIT(9)
54 #define SCTLR_M_BIT BIT(0)
55 #define SCTLR_A_BIT BIT(1)
56 #define SCTLR_C_BIT BIT(2)
57 #define SCTLR_SA_BIT BIT(3)
[all …]
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| D | gic_v3.h | 285 rwp_mask = BIT(GICR_CTLR_RWP); in GIC_WaitRWP()
288 rwp_mask = BIT(GICD_CTLR_RWP); in GIC_WaitRWP()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/ |
| D | fsl_misc_soc.c | 23 scr = BIT(5); in SOC_MixPowerInit()
27 aonmix_base->LP_HANDSHAKE |= BIT(13); in SOC_MixPowerInit()
32 scr = BIT(4); in SOC_MixPowerInit()
37 scr = BIT(6); in SOC_MixPowerInit()
47 mix_base->AUTHEN_CTRL |= BIT(9); in SOC_MixPowerInit()
49 mix_base->PSW_ACK_CTRL_0 &= ~(BIT(28) | BIT(29)); in SOC_MixPowerInit()
55 mem_regs->mem_ctrl |= BIT(2); in SOC_MixPowerInit()
64 mix_base->SLICE_SW_CTRL |= BIT(31); in SOC_MixPowerInit()
79 mix_base->SLICE_SW_CTRL |= BIT(31); in SOC_MixPowerInit()
86 mix_base->SLICE_SW_CTRL &= ~BIT(31); in SOC_MixPowerInit()
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| D | fsl_misc_soc.h | 24 #ifndef BIT
25 #define BIT(x) (1U << x) macro
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/incl/ |
| D | mlan_11k.h | 117 #ifndef BIT
118 #define BIT(x) (1 << (x)) macro
155 #define WLAN_RRM_REPORT_MODE_REJECT_LATE BIT(0)
156 #define WLAN_RRM_REPORT_MODE_REJECT_INCAPABLE BIT(1)
157 #define WLAN_RRM_REPORT_MODE_REJECT_REFUSED BIT(2)
168 #define WLAN_RRM_MEAS_REQUEST_MODE_PARALLEL BIT(0)
169 #define WLAN_RRM_MEAS_REQUEST_MODE_ENABLE BIT(1)
170 #define WLAN_RRM_MEAS_REQUEST_MODE_REQUEST BIT(2)
171 #define WLAN_RRM_MEAS_REQUEST_MODE_REPORT BIT(3)
172 #define WLAN_RRM_MEAS_REQUEST_MODE_DURATION_MANDATORY BIT(4)
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/lin/ |
| D | lin_driver.c | 35 static inline uint8_t BIT(const uint8_t A, uint8_t B) in BIT() function
713 …((uint8_t)((uint8_t)((uint8_t)((uint8_t)(BIT(PID, 0U) ^ BIT(PID, 1U)) ^ BIT(PID, 2U)) ^ BIT(PID, 4… in LIN_ProcessParity()
715 …((uint8_t)(~(uint8_t)((uint8_t)((uint8_t)(BIT(PID, 1U) ^ BIT(PID, 3U)) ^ BIT(PID, 4U)) ^ BIT(PID, … in LIN_ProcessParity()
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| D | fsl_lin.c | 54 static inline uint8_t BIT(const uint8_t A, uint8_t B) in BIT() function
800 …((uint8_t)((uint8_t)((uint8_t)((uint8_t)(BIT(PID, 0U) ^ BIT(PID, 1U)) ^ BIT(PID, 2U)) ^ BIT(PID, 4… in LIN_ProcessParity()
802 …((uint8_t)(~(uint8_t)((uint8_t)((uint8_t)(BIT(PID, 1U) ^ BIT(PID, 3U)) ^ BIT(PID, 4U)) ^ BIT(PID, … in LIN_ProcessParity()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/elemu/ |
| D | fsl_elemu.c | 32 #ifdef BIT
33 #undef BIT
35 #define BIT(x) (((uint32_t)1u << (x))) macro
51 uint32_t mask = (BIT(regid)); in ELEMU_mu_hal_send_data()
60 uint32_t mask = BIT(regid); in ELEMU_mu_hal_receive_data()
75 uint32_t mask = BIT(regid); in ELEMU_mu_hal_receive_data_wait()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/drivers/ |
| D | fsl_bitaccess.h | 60 #define BME_BFI_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) argument
61 #define BME_UBFX_MASK(BIT,WIDTH) (1<<28) | (BIT<<23) | ((WIDTH-1)<<19) argument
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93evk/ |
| D | board.h | 73 #define BIT(n) (1U << (n)) macro
92 #define DDR_RETENTION_A55_FLAG BIT(0)
93 #define DDR_RETENTION_M33_FLAG BIT(1)
94 #define DDR_RETENTION_PLL_LPM BIT(2)
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| D | board.c | 484 while ((read_data & BIT(1)) == 0x0) in BOARD_Ipg_Stop_Ack_Wait()
493 while ((read_data & BIT(1)) != 0x0) in BOARD_Ipg_Stop_Ack_Wait()
579 while (R32(DRAM_APB_CLK + 0x20) & BIT(28)) in BOARD_DDR_Disable_Bypass()
636 W32(ddrc_cfg->reg, ddrc_cfg->val & ~BIT(4)); in BOARD_DDRC_Restore()
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/ |
| D | board.c | 342 bool epdc_disable = !!(val & BIT(23)); in BOARD_GetSocVariantType()
343 bool core1_disable = !!(val & BIT(15)); in BOARD_GetSocVariantType()
347 if ((val & (BIT(18) | BIT(19))) == (BIT(18) | BIT(19))) in BOARD_GetSocVariantType()
1841 while (!(R32(pll4[8][0]) & BIT(24))) in BOARD_LpavInit()
1846 W32(pll4[9][0], pll4[9][1] & ~(BIT(31) | BIT(23) | BIT(15) | BIT(7))); in BOARD_LpavInit()
2126 SETBIT32(LPDDR_BASE + DENALI_CTL_144, BIT(3) << LPI_WAKEUP_EN_SHIFT); in BOARD_DramEnterRetention()
2184 …CLRBIT32(LPDDR_BASE + DENALI_PI_132, BIT(16)); /* PI_MC_PWRUP_SELF_REF_EXIT = 0 … in BOARD_DramExitRetention()
2209 … CLRBIT32(LPDDR_BASE + DENALI_PI_132, BIT(16)); /* PI_MC_PWRUP_SELF_REF_EXIT=0 */ in BOARD_DramExitRetention()
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| D | board.h | 22 #ifndef BIT
23 #define BIT(n) (1U << (n)) macro
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93qsb/ |
| D | board.h | 57 #define BIT(n) (1U << (n)) macro
75 #define DDR_RETENTION_A55_FLAG BIT(0)
76 #define DDR_RETENTION_M33_FLAG BIT(1)
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| D | board.c | 442 while ((read_data & BIT(1)) == 0x0) in BOARD_Ipg_Stop_Ack_Wait()
451 while ((read_data & BIT(1)) != 0x0) in BOARD_Ipg_Stop_Ack_Wait()
537 while (R32(DRAM_APB_CLK + 0x20) & BIT(28)) in BOARD_DDR_Disable_Bypass()
594 W32(ddrc_cfg->reg, ddrc_cfg->val & ~BIT(4)); in BOARD_DDRC_Restore()
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| /hal_nxp-latest/mcux/mcux-sdk/boards/mcimx93autoevk/ |
| D | board.h | 67 #define BIT(n) (1U << (n)) macro
85 #define DDR_RETENTION_A55_FLAG BIT(0)
86 #define DDR_RETENTION_M33_FLAG BIT(1)
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| D | board.c | 455 while ((read_data & BIT(1)) == 0x0) in BOARD_Ipg_Stop_Ack_Wait()
464 while ((read_data & BIT(1)) != 0x0) in BOARD_Ipg_Stop_Ack_Wait()
550 while (R32(DRAM_APB_CLK + 0x20) & BIT(28)) in BOARD_DDR_Disable_Bypass()
607 W32(ddrc_cfg->reg, ddrc_cfg->val & ~BIT(4)); in BOARD_DDRC_Restore()
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/incl/wps/ |
| D | wifi_nxp_wps.h | 98 #ifndef BIT
99 #define BIT(x) (1 << (x)) macro
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| /hal_nxp-latest/mcux/mcux-sdk/components/sdu/ |
| D | fsl_adapter_sdu.c | 206 #ifndef BIT
207 #define BIT(n) (1U << (n)) macro
210 #define SDU_DBG_LEVEL_WARN BIT(3U)
211 #define SDU_DBG_LEVEL_ERROR BIT(2U)
212 #define SDU_DBG_LEVEL_DEBUG BIT(1U)
213 #define SDU_DBG_LEVEL_DUMP BIT(0U)
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| /hal_nxp-latest/mcux/mcux-sdk/components/video/display/it6161/ |
| D | fsl_it6161.h | 66 #ifndef BIT
67 #define BIT(nr) ((0x01U) << (nr)) macro
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| D | hdmi_tx.c | 818 ptr[0] |= BIT(4); in HDMI_AviInfoframePack()
824 ptr[0] |= BIT(3); in HDMI_AviInfoframePack()
829 ptr[0] |= BIT(2); in HDMI_AviInfoframePack()
840 ptr[2] |= BIT(7); in HDMI_AviInfoframePack()
955 ptr[4] |= BIT(7); in HDMI_AudioInfoframePack()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma_rev2/ |
| D | fsl_edma_rev2.h | 93 #define EDMA_TCD_CH_INT_MASK BIT(1)
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/wifidriver/ |
| D | mlan_11k.c | 84 bits_field[bit / 8U] |= BIT(bit % 8U); in wlan_rrm_bit_field_set()
94 return ((bit_field[bit / (t_u8)8U] & (t_u8)(BIT((bit % 8U)))) != (t_u8)0U); in wlan_rrm_bit_field_is_set()
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/incl/wifidriver/ |
| D | wifi-decl.h | 705 #ifndef BIT
706 #define BIT(n) (1U << (n)) macro
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/wlcmgr/ |
| D | wlan_enhanced_tests.c | 1673 (req_typ & BIT(4)) ? "Trigger":"No trigger",
1674 (req_typ & BIT(6)) ? "Unannounced":"Announced",
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