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Searched refs:ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h5645 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5648 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1175_cm7.h5648 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5651 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h5639 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5642 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1165_cm4.h5636 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5639 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h5648 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5651 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h5651 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5654 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1166_cm7.h5654 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5657 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h5657 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5660 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1173_cm7.h5660 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5663 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h5663 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5666 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h5665 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5668 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1176_cm4.h5662 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
5665 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/
DMIMXRT1182.h4445 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4448 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/
DMIMXRT1181.h4445 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4448 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/
DMIMXRT1187_cm33.h4548 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4551 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1187_cm7.h4445 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4448 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/
DMIMXRT1189_cm33.h4547 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4550 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
DMIMXRT1189_cm7.h4444 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) macro
4447 …int32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)