Home
last modified time | relevance | path

Searched refs:AHBSC_RAMG_MEM_RULE_RULE3_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h2765 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2773 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
DMCXN546_cm33_core1.h2765 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2773 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h2765 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2773 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
DMCXN547_cm33_core1.h2765 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2773 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h2799 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2807 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
DMCXN947_cm33_core0.h2799 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2807 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h2799 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2807 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)
DMCXN946_cm33_core1.h2799 #define AHBSC_RAMG_MEM_RULE_RULE3_MASK (0x3000U) macro
2807 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMG_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMG_MEM_RULE_RULE3_MASK)