Home
last modified time | relevance | path

Searched refs:AHBSC_RAMC_MEM_RULE_RULE0_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h2894 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2902 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/
DMCXN235.h2876 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2884 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h2387 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2395 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
DMCXN546_cm33_core1.h2387 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2395 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h2387 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2395 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
DMCXN547_cm33_core1.h2387 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2395 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h2421 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2429 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
DMCXN947_cm33_core0.h2421 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2429 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h2421 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2429 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)
DMCXN946_cm33_core1.h2421 #define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) macro
2429 …(((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK)