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Searched refs:ADC_MCR_ADCLKSEL_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Adc/src/
DAdc_Sar_Ip.c931 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_CollectMcrMasks()
2070 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_CalibrationClkSelect()
2098 uint32 AdcClkSel = McrSavedValue & ADC_MCR_ADCLKSEL_MASK; in Adc_Sar_CalibrationClkRestore()
2110 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_CalibrationClkRestore()
3024 AdcClkSel = ((*MCRAddr) & ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
3026 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
3173 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
4102 *MCRAddr = ((*MCRAddr) & ~(ADC_MCR_ADCLKSEL_MASK)) | Mcr; in Adc_Sar_Ip_SetClockMode()
/hal_nxp-latest/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c894 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_CollectMcrMasks()
2813 AdcClkSel = ((*MCRAddr) & ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
2815 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
2954 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_SelfTest()
3233 AdcClkSel = (Mcr & ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_DoCalibration()
3234 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_DoCalibration()
3330 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK); in Adc_Sar_Ip_DoCalibration()
3870 *MCRAddr = ((*MCRAddr) & ~(ADC_MCR_ADCLKSEL_MASK)) | Mcr; in Adc_Sar_Ip_SetClockMode()
/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip_HeaderWrapper_S32XX.h152 #define ADC_MCR_ADCLKSEL_MASK ADC_MCR_ADCLKSE_MASK macro
DAdc_Sar_Ip_HeaderWrapper_S32XX_AE.h148 #define ADC_MCR_ADCLKSEL_MASK ADC_MCR_ADCLKSE_MASK macro
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_ADC.h206 #define ADC_MCR_ADCLKSEL_MASK (0x6U) macro
209 … (((uint32_t)(((uint32_t)(x)) << ADC_MCR_ADCLKSEL_SHIFT)) & ADC_MCR_ADCLKSEL_MASK)