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Searched refs:SYS_PLL2_CTRL (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
247 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
254 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2286 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2317 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
246 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
252 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
257 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2251 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2282 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
247 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
254 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2286 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2317 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
247 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
254 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2286 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2317 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
247 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
254 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2286 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2317 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
246 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
252 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
257 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2251 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2282 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_clock.c200 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) in CLOCK_InitSysPll2()
208 if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) in CLOCK_InitSysPll2()
210 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; in CLOCK_InitSysPll2()
213 if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) in CLOCK_InitSysPll2()
215 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; in CLOCK_InitSysPll2()
227 reg = ANADIG_PLL->SYS_PLL2_CTRL; in CLOCK_InitSysPll2()
233 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
247 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
254 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
259 ANADIG_PLL->SYS_PLL2_CTRL = reg; in CLOCK_InitSysPll2()
[all …]
Dfsl_clock.h2286 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> in CLOCK_IsPllBypassed()
2317 return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> in CLOCK_IsPllEnabled()
/hal_nxp-3.7.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c889 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
937 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
/hal_nxp-3.7.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c889 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
937 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
/hal_nxp-3.7.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c889 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
937 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
/hal_nxp-3.7.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c889 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
937 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
/hal_nxp-3.7.0/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c889 ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
937 ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK; in RT1170_SetClockSourcesControlBySetpoint()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h5177 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h5177 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member
DMIMXRT1175_cm4.h5174 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h5168 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member
DMIMXRT1165_cm4.h5165 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h5183 __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ member

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