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Searched refs:SYSCON_AHBCLKDIV_DIV_MASK (Results 1 – 25 of 54) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC55S36/drivers/
Dfsl_power.c3074 ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) != 0UL)) in POWER_SetSystemClock12MHZ()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5536/drivers/
Dfsl_power.c3074 ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) != 0UL)) in POWER_SetSystemClock12MHZ()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5534/drivers/
Dfsl_power.c3074 ((SYSCON->AHBCLKDIV & SYSCON_AHBCLKDIV_DIV_MASK) != 0UL)) in POWER_SetSystemClock12MHZ()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h8464 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
8468 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h9186 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
9190 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm4.h9185 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
9189 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
DLPC54114_cm0plus.h9172 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
9176 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h14075 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
14079 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h13425 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
13429 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h14069 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
14073 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h13283 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
13287 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h17648 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
17652 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h17573 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
17577 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h16477 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
16480 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h22483 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
22487 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h18968 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18972 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h22330 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
22334 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h22483 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
22487 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h18176 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18180 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h18968 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18972 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h22330 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
22334 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h18176 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18180 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h17183 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
17186 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h18293 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18297 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h18494 #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) macro
18498 … (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)

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