Searched refs:Predivider (Results 1 – 7 of 7) sorted by relevance
222 Value |= (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()366 Value |= (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPlldigRdivMfiMfnSdmen()480 RegValue |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U)); in Clock_Ip_ResetLfastPLL()539 …p_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U)); in Clock_Ip_SetLfastPLL()
198 Value |= (uint32) (PLL_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()337 Value |= (uint32) (PLL_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPllRdivMfiMfnOdiv2Sdmen()
295 IP_SCG->SPLLCFG |= SCG_SPLLCFG_PREDIV((uint32)(Config->Predivider) - 1U) | in Clock_Ip_SetSpll_TrustedCall()
620 …SpllConfiguration.Predivider = (uint8)((IP_SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_… in getSpllConfig()
2983 uint8 Predivider; /**< Input clock predivider. */ member
2967 uint8 Predivider; /**< Input clock predivider. */ member
3069 uint8 Predivider; /**< Input clock predivider. */ member
