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Searched refs:PSCCTL0_SET (Results 1 – 25 of 28) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_power.c686 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
840 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in AT_QUICKACCESS_SECTION_CODE()
1041 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_USB_MASK; in POWER_InitPowerConfig()
1283 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK; in POWER_DisableGDetVSensors()
1358 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK; in POWER_EnableGDetVSensors()
1454 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in POWER_TrimSvc()
Dfsl_clock.c289 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
298 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_power.c686 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in AT_QUICKACCESS_SECTION_CODE()
840 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in AT_QUICKACCESS_SECTION_CODE()
1041 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_USB_MASK; in POWER_InitPowerConfig()
1283 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK; in POWER_DisableGDetVSensors()
1358 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_ELS_MASK; in POWER_EnableGDetVSensors()
1454 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_AON_MEM_MASK; in POWER_TrimSvc()
Dfsl_clock.c289 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
298 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/boards/evkmimxrt595/
Dboard.c294 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in BOARD_DeinitFlash()
383 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in BOARD_SetFlexspiClock()
408 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in BOARD_SetFlexspiClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/boards/rdrw612bga/
Dboard.c304 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_DeinitFlash()
396 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; in BOARD_SetFlexspiClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/boards/mimxrt685audevk/
Dboard.c291 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in BOARD_DeinitXip()
385 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in BOARD_SetFlexspiClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/boards/evkmimxrt685/
Dboard.c298 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in BOARD_DeinitXip()
392 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in BOARD_SetFlexspiClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/sdu/
Dfsl_sdioslv_sdu.c76 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_SDIO(1); in SDIOSLV_Init0()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.h892 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
Dfsl_power.c703 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.h892 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
901 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
Dfsl_power.c703 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.h1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.h1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c704 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
711 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK; in AT_QUICKACCESS_SECTION_CODE()
Dfsl_clock.h1105 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
1114 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); in CLOCK_EnableClock()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h1232 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
2718 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
DMIMXRT685S_cm33.h6943 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
8448 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h6943 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
8448 __O uint32_t PSCCTL0_SET; /**< clock set register 0, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h1909 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
4108 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
DMIMXRT595S_cm33.h8147 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
10365 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h8143 __O uint32_t PSCCTL0_SET; /**< Clock Control 0 Set, offset: 0x40 */ member
10361 __IO uint32_t PSCCTL0_SET; /**< Clock Set 0, offset: 0x40 */ member

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