Searched refs:PLLSR (Results 1 – 6 of 6) sorted by relevance
1389 …return (((IP_CORE_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_… in Clock_Ip_Get_COREPLL_CLK_Frequency()1399 …return (((IP_PERIPH_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Cloc… in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1409 …return (((IP_DDR_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_I… in Clock_Ip_Get_DDRPLL_CLK_Frequency()1423 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1425 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS0_Frequency()1433 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS1_Frequency()1435 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS1_Frequency()1443 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS2_Frequency()1445 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS2_Frequency()1453 …E_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVP… in Clock_Ip_Get_COREPLL_DFS3_Frequency()[all …]
263 …PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG… in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()399 …PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG… in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()
247 …PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR… in Clock_Ip_CompletePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()367 …PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR… in Clock_Ip_CompletePllRdivMfiMfnOdiv2Sdmen()
1804 …return (((IP_PLL->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PLL_C… in Clock_Ip_Get_PLL_CLK_Frequency()1814 …return (((IP_PLL_AUX->PLLSR & PLL_PLLSR_LOCK_MASK) >> PLL_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32P… in Clock_Ip_Get_PLLAUX_CLK_Frequency()
77 __IO uint32_t PLLSR; /**< PLL Status, offset: 0x4 */ member
