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Searched refs:PLLDIG_PLLDV_RDIV_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.7.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Specific.c263 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
274 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
307 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
330 RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SpecificPlatformInitClock()
DClock_Ip_Pll.c221 Value &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
365 Value &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK); in Clock_Ip_SetPlldigRdivMfiMfnSdmen()
DClock_Ip_Frequency.c4092 …Rdiv = ((Base->PLLDV & PLLDIG_PLLDV_RDIV_MASK) >> PLLDIG_PLLDV_RDIV_SHIFT); /* Rdiv */ in PLL_VCO()
/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_PLLDIG.h148 #define PLLDIG_PLLDV_RDIV_MASK (0x7000U) macro
151 … (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLDV_RDIV_SHIFT)) & PLLDIG_PLLDV_RDIV_MASK)