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Searched refs:MU_CR_MUR_MASK (Results 1 – 25 of 53) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/mu/
Dfsl_mu.h600 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; in MU_ResetBothSides()
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/mu1/
Dfsl_mu.h714 base->CR |= MU_CR_MUR_MASK; in MU_ResetBothSides()
/hal_nxp-3.7.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MU.h174 #define MU_CR_MUR_MASK (0x1U) macro
177 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MU.h230 #define MU_CR_MUR_MASK (0x1U) macro
233 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h13716 #define MU_CR_MUR_MASK (0x20U) macro
13722 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
DK32L3A60_cm4.h13812 #define MU_CR_MUR_MASK (0x20U) macro
13818 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h19371 #define MU_CR_MUR_MASK (0x20U) macro
19377 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h19372 #define MU_CR_MUR_MASK (0x20U) macro
19378 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h22934 #define MU_CR_MUR_MASK (0x20U) macro
22940 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h22934 #define MU_CR_MUR_MASK (0x20U) macro
22940 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h32847 #define MU_CR_MUR_MASK (0x20U) macro
32853 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_cm33.h34474 #define MU_CR_MUR_MASK (0x20U) macro
34480 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h34473 #define MU_CR_MUR_MASK (0x20U) macro
34479 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h70244 #define MU_CR_MUR_MASK (0x20U) macro
70246 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
DMIMX8QM6_dsp.h75581 #define MU_CR_MUR_MASK (0x20U) macro
75587 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h56941 #define MU_CR_MUR_MASK (0x20U) macro
56947 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h56941 #define MU_CR_MUR_MASK (0x20U) macro
56947 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h56417 #define MU_CR_MUR_MASK (0x20U) macro
56423 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h60325 #define MU_CR_MUR_MASK (0x20U) macro
60331 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h60849 #define MU_CR_MUR_MASK (0x20U) macro
60855 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h60846 #define MU_CR_MUR_MASK (0x20U) macro
60852 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h71516 #define MU_CR_MUR_MASK (0x20U) macro
71522 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_ca53.h68640 #define MU_CR_MUR_MASK (0x20U) macro
68646 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h65728 #define MU_CR_MUR_MASK (0x1U) macro
65734 #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
DMIMX9352_ca55.h57277 #define MU_CR_MUR_MASK (0x1U) macro
57283 …(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)

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