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Searched refs:L1SYSTEMBUSCACHE_LINESIZE_BYTE (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm4/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm4/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm4/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro
/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/cache/lmem/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm4/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm4/
Dfsl_cache.c277 … address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ in L1CACHE_InvalidateSystemCacheByRange()
292 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_InvalidateSystemCacheByRange()
329 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanSystemCacheByRange()
344 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanSystemCacheByRange()
382 …address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ in L1CACHE_CleanInvalidateSystemCacheByRange()
397 startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; in L1CACHE_CleanInvalidateSystemCacheByRange()
Dfsl_cache.h31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ macro