| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/epdc/ |
| D | fsl_epdc.h | 508 base->IRQ_MASK.SET = ((uint32_t)interrupts << 16U); in EPDC_EnableInterrupts()
520 base->IRQ_MASK.CLR = ((uint32_t)interrupts << 16U); in EPDC_DisableInterrupts()
532 return (uint8_t)(base->IRQ_MASK.RW >> 16U); in EPDC_GetEnabledInterrupts()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/mipi_dsi/ |
| D | fsl_mipi_dsi.h | 505 base->IRQ_MASK &= ~intGroup1; in DSI_EnableInterrupts()
520 base->IRQ_MASK |= intGroup1; in DSI_DisableInterrupts()
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| D | fsl_mipi_dsi.c | 462 base->IRQ_MASK = 0xFFFFFFFFU; in DSI_Init()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/mipi_dsi_split/ |
| D | fsl_mipi_dsi.h | 508 base->apb->IRQ_MASK &= ~intGroup1; in DSI_EnableInterrupts()
523 base->apb->IRQ_MASK |= intGroup1; in DSI_DisableInterrupts()
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| D | fsl_mipi_dsi.c | 467 base->apb->IRQ_MASK = 0xFFFFFFFFU; in DSI_Init()
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| /hal_nxp-3.7.0/mcux/mcux-sdk/drivers/mipi_csi2rx/ |
| D | fsl_mipi_csi2rx.h | 35 #define CSI2RX_REG_IRQ_MASK(base) (base)->IRQ_MASK
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| /hal_nxp-3.7.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 14503 …__IO uint32_t IRQ_MASK; /**< EPDC IRQ Mask Register, offset: 0x400 … member
14788 #define EPDC_IRQ_MASK_REG(base) ((base)->IRQ_MASK)
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 30342 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
56573 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm7.h | 30342 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
56573 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| D | MIMXRT1175_cm4.h | 30340 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
57388 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm7.h | 30030 __IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x28 */ member
56049 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| D | MIMXRT1165_cm4.h | 30028 __IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x28 */ member
56864 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm7.h | 32035 __IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x28 */ member
59957 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| D | MIMXRT1166_cm4.h | 32033 __IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x28 */ member
60772 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 32347 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
60481 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm4.h | 32342 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
61293 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| D | MIMXRT1173_cm7.h | 32344 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
60478 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 26380 __IO uint32_t IRQ_MASK; /**< Mask interrupt, offset: 0x2A8 */ member
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| D | MIMXRT595S_cm33.h | 33423 __IO uint32_t IRQ_MASK; /**< Mask interrupt, offset: 0x2A8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 32349 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
71148 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| D | MIMXRT1176_cm4.h | 32347 __IO uint32_t IRQ_MASK; /**< offset: 0x28 */ member
71963 __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 17780 } IRQ_MASK; member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 33422 __IO uint32_t IRQ_MASK; /**< Mask interrupt, offset: 0x2A8 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD3/ |
| D | MIMX8UD3_cm33.h | 14720 } IRQ_MASK; member
35880 __IO uint32_t IRQ_MASK; /**< offset: 0x2A8 */ member
50140 __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ member
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| /hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMX8UD7/ |
| D | MIMX8UD7_cm33.h | 14720 } IRQ_MASK; member
35880 __IO uint32_t IRQ_MASK; /**< offset: 0x2A8 */ member
50140 __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ member
|
