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Searched refs:I3C01FCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h613 #define I3C01FCLKDIV_OFFSET 0x810 macro
983 … kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h613 #define I3C01FCLKDIV_OFFSET 0x810 macro
983 … kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h613 #define I3C01FCLKDIV_OFFSET 0x810 macro
983 … kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKDIV_OFFSET, 0), /*!< I3c Clk Divider. */