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Searched refs:CTIMER_CCR_CAP0I_MASK (Results 1 – 25 of 66) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/ctimer/
Dfsl_ctimer.h94 kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
386 base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_EnableInterrupts()
411 base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_DisableInterrupts()
440 enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK in CTIMER_GetEnabledInterrupts()
Dfsl_ctimer.c458 (uint32_t)CTIMER_CCR_CAP0I_MASK) in CTIMER_SetupCapture()
466 reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); in CTIMER_SetupCapture()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC802/
DLPC802.h1395 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1399 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC804/
DLPC804.h1777 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1781 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC844/
DLPC844.h1479 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1483 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC845/
DLPC845.h1885 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1889 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h1487 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1491 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h1455 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1459 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm4.h1454 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1458 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
DLPC54114_cm0plus.h1443 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1447 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h2122 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
2126 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h1718 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1722 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h1715 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1719 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h1714 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
1718 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h3259 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3263 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h3184 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3188 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h2965 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
2968 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h6604 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
6608 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h3665 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3669 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h6559 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
6563 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h6604 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
6608 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h3257 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3261 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h3665 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3669 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h6559 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
6563 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h3257 #define CTIMER_CCR_CAP0I_MASK (0x4U) macro
3261 … (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)

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