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Searched refs:CHANEN (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/dmic/
Dfsl_dmic_dma.c243 base->CHANEN &= ~(1UL << (handle->channel)); in DMIC_TransferAbortReceiveDMA()
Dfsl_dmic.c228 base->CHANEN |= channelmask; in DMIC_EnableChannnel()
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h2236 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm4.h2235 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
DLPC54114_cm0plus.h2224 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h2984 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h2580 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h2577 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h2576 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h4121 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h4046 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h3821 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h4527 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h4527 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h4186 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h4117 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h4042 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h6549 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
DMIMXRT685S_cm33.h12416 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h12416 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h11790 __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ member
/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h11483 __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ member

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