/hal_nxp-3.7.0/mcux/mcux-sdk/drivers/dmic/ |
D | fsl_dmic_dma.c | 243 base->CHANEN &= ~(1UL << (handle->channel)); in DMIC_TransferAbortReceiveDMA()
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D | fsl_dmic.c | 228 base->CHANEN |= channelmask; in DMIC_EnableChannnel()
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54113/ |
D | LPC54113.h | 2236 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54114/ |
D | LPC54114_cm4.h | 2235 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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D | LPC54114_cm0plus.h | 2224 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S005/ |
D | LPC54S005.h | 2984 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54605/ |
D | LPC54605.h | 2580 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54607/ |
D | LPC54607.h | 2577 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54005/ |
D | LPC54005.h | 2576 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54616/ |
D | LPC54616.h | 4121 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54606/ |
D | LPC54606.h | 4046 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54016/ |
D | LPC54016.h | 3821 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018M/ |
D | LPC54S018M.h | 4527 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018M/ |
D | LPC54018M.h | 4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S018/ |
D | LPC54S018.h | 4527 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54018/ |
D | LPC54018.h | 4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54S016/ |
D | LPC54S016.h | 4186 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54618/ |
D | LPC54618.h | 4119 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54628/ |
D | LPC54628.h | 4117 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC54608/ |
D | LPC54608.h | 4042 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT685S/ |
D | MIMXRT685S_dsp.h | 6549 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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D | MIMXRT685S_cm33.h | 12416 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT633S/ |
D | MIMXRT633S.h | 12416 __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/LPC5534/ |
D | LPC5534.h | 11790 __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ member
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/hal_nxp-3.7.0/mcux/mcux-sdk/devices/MIMXRT595S/ |
D | MIMXRT595S_dsp.h | 11483 __IO uint32_t CHANEN; /**< Channel Enable, offset: 0xF00 */ member
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