| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/puf_v3/ |
| D | fsl_puf_v3.c | 49 while (0u == base->SR) in puf_waitForInit()
54 while ((base->SR & PUF_SR_BUSY_MASK) != 0u) in puf_waitForInit()
59 if (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK)) in puf_waitForInit()
96 if ((result == kPUF_ResultOK) && (0u == (base->SR & PUF_SR_ERROR_MASK))) in puf_makeStatus()
233 while (0u != (base->SR & PUF_SR_BUSY_MASK)) in PUF_Enroll()
235 if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) in PUF_Enroll()
248 if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) in PUF_Enroll()
310 while (0u != (base->SR & PUF_SR_BUSY_MASK)) in PUF_Start()
312 if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) in PUF_Start()
333 if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) in PUF_Start()
[all …]
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| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/mu/ |
| D | fsl_mu.c | 91 while (0U == (base->SR & (((uint32_t)kMU_Tx0EmptyFlag) >> regIndex))) in MU_SendMsg()
113 while (0U == (base->SR & (((uint32_t)kMU_Rx0FullFlag) >> regIndex))) in MU_ReceiveMsg()
137 while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK))) in MU_SetFlags()
203 base->SR = MU_SR_RDIP_MASK; in MU_BootCoreB()
295 base->SR = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); in MU_HardwareResetOtherCore()
304 while (0U == (base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()
315 while (0U == (base->SR & MU_SR_RDIP_MASK)) in MU_HardwareResetOtherCore()
384 base->SR = resetFlag; in MU_HardwareResetOtherCore()
394 while (0U == (base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()
407 while (0U == (base->SR & MU_SR_RDIP_MASK)) in MU_HardwareResetOtherCore()
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| D | fsl_mu.h | 320 return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; in MU_GetFlags()
355 …return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_… in MU_GetStatusFlags()
385 return (base->SR & irqMask); in MU_GetInterruptsPending()
434 base->SR = (mask & regMask); in MU_ClearStatusFlags()
513 base->SR = MU_SR_NMIC_MASK; in MU_ClearNmi()
603 while (0U != (base->SR & MU_SR_RS_MASK)) in MU_ResetBothSides()
739 uint32_t ret = (base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT; in MU_GetOtherCorePowerMode()
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| /hal_nxp-3.6.0/imx/drivers/ |
| D | mu_imx.h | 195 return (bool)(base->SR & (MU_SR_TE0_MASK >> index)); in MU_IsTxEmpty()
281 return (bool)(base->SR & (MU_SR_RF0_MASK >> index)); in MU_IsRxFull()
381 return (bool)(base->SR & (MU_SR_GIP0_MASK >> index)); in MU_IsGeneralIntPending()
394 base->SR = (MU_SR_GIP0_MASK >> index); in MU_ClearGeneralIntPending()
473 return (bool)(base->SR & MU_SR_FUP_MASK); in MU_IsFlagPending()
486 return base->SR & MU_SR_Fn_MASK; in MU_GetFlags()
506 return (mu_power_mode_t)((base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT); in MU_GetOtherCorePowerMode()
522 return (bool)(base->SR & MU_SR_EP_MASK); in MU_IsEventPending()
553 return base->SR & statusToCheck; in MU_GetMsgStatus()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/main/ |
| D | ipc_imx8qm.c | 100 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
117 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
147 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
157 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/main/ |
| D | ipc_imx8qx.c | 96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U) in sc_ipc_read()
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U) in sc_ipc_read()
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U) in sc_ipc_write()
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U) in sc_ipc_write()
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| /hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/ |
| D | Clock_Ip_Monitor.c | 246 FrequencyCheckStatus = (CmuFc->SR & CMU_FC_SR_RS_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
267 CmuFc->SR |= (CMU_FC_SR_FLL_MASK | CMU_FC_SR_FHH_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
421 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_GetInterruptStatus()
444 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_ClockFailInt()
458 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
469 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/ |
| D | Clock_Ip_Monitor.c | 278 FrequencyCheckStatus = (CmuFc->SR & CMU_FC_SR_RS_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
299 CmuFc->SR |= (CMU_FC_SR_FLL_MASK | CMU_FC_SR_FHH_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
454 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_GetInterruptStatus()
477 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_ClockFailInt()
491 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
502 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
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| /hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/ |
| D | Clock_Ip_Monitor.c | 246 FrequencyCheckStatus = (CmuFc->SR & CMU_FC_SR_RS_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
267 CmuFc->SR |= (CMU_FC_SR_FLL_MASK | CMU_FC_SR_FHH_MASK); in Clock_Ip_DisableCmuFcFceRefCntLfrefHfref()
441 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_GetInterruptStatus()
464 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK; in Clock_Ip_CMU_ClockFailInt()
478 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
489 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue; in Clock_Ip_CMU_ClockFailInt()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/mcuxpresso/ |
| D | boot_multicore_slave.c | 40 __IO uint32_t SR; /**< Status Register, offset: 0x60 */ member
130 MUA->SR = MU_SR_RDIP_MASK; in boot_multicore_slave()
138 while (!(MUA->SR & MU_SR_RDIP_MASK)) in boot_multicore_slave()
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| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/rtc/ |
| D | fsl_rtc.c | 620 if (0U != (RTC_SR_TIF_MASK & base->SR)) in RTC_GetStatusFlags()
624 if (0U != (RTC_SR_TOF_MASK & base->SR)) in RTC_GetStatusFlags()
628 if (0U != (RTC_SR_TAF_MASK & base->SR)) in RTC_GetStatusFlags()
633 if (0U != (RTC_SR_MOF_MASK & base->SR)) in RTC_GetStatusFlags()
643 if (0U != (RTC_SR_TIDF_MASK & base->SR)) in RTC_GetStatusFlags()
873 if (0U != (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK))) in RTC_IncrementMonotonicCounter()
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| D | fsl_rtc.h | 178 base->SR &= ~RTC_SR_TCE_MASK; in RTC_Deinit()
363 base->SR |= RTC_SR_TCE_MASK; in RTC_StartTimer()
375 base->SR &= ~RTC_SR_TCE_MASK; in RTC_StopTimer()
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