Home
last modified time | relevance | path

Searched refs:SPI_SR_TFFF_MASK (Results 1 – 25 of 35) sorted by relevance

12

/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/dspi/
Dfsl_dspi.h51 kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/
55 …tusFlag = (int)(SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK |
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SPI.h420 #define SPI_SR_TFFF_MASK (0x2000000U) macro
423 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h9366 #define SPI_SR_TFFF_MASK (0x2000000U) macro
9372 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h9399 #define SPI_SR_TFFF_MASK (0x2000000U) macro
9405 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h9302 #define SPI_SR_TFFF_MASK (0x2000000U) macro
9308 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h10338 #define SPI_SR_TFFF_MASK (0x2000000U) macro
10344 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h10185 #define SPI_SR_TFFF_MASK (0x2000000U) macro
10191 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h11126 #define SPI_SR_TFFF_MASK (0x2000000U) macro
11132 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h11256 #define SPI_SR_TFFF_MASK (0x2000000U) macro
11262 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h11644 #define SPI_SR_TFFF_MASK (0x2000000U) macro
11650 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h11451 #define SPI_SR_TFFF_MASK (0x2000000U) macro
11457 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4_extension.h22263 …se, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF…
22284 …se, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF…
22302 #define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
22306 #define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR…
22329 …_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF…
22352 …_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF…
22373 …SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF…
22393 …W_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF…
DMKW40Z4.h7577 #define SPI_SR_TFFF_MASK 0x2000000u macro
7580 …FF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h12571 #define SPI_SR_TFFF_MASK (0x2000000U) macro
12577 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h12969 #define SPI_SR_TFFF_MASK (0x2000000U) macro
12975 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h7021 #define SPI_SR_TFFF_MASK (0x2000000U) macro
7023 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h7021 #define SPI_SR_TFFF_MASK (0x2000000U) macro
7023 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h17238 #define SPI_SR_TFFF_MASK (0x2000000U) macro
17244 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h20921 #define SPI_SR_TFFF_MASK (0x2000000U) macro
20927 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h6843 #define SPI_SR_TFFF_MASK (0x2000000U) macro
6845 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h22732 #define SPI_SR_TFFF_MASK (0x2000000U) macro
22738 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h22778 #define SPI_SR_TFFF_MASK (0x2000000U) macro
22784 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h6772 #define SPI_SR_TFFF_MASK (0x2000000U) macro
6774 …) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h7577 #define SPI_SR_TFFF_MASK 0x2000000u macro
7580 …FF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h7577 #define SPI_SR_TFFF_MASK 0x2000000u macro
7580 …FF(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)

12