Searched refs:SIM_SCGC5_TMR1_MASK (Results 1 – 5 of 5) sorted by relevance
10080 #define SIM_SCGC5_TMR1_MASK (0x1000000U) macro10086 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK)
14785 #define SIM_SCGC5_TMR1_MASK (0x1000000U) macro14791 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK)
14781 #define SIM_SCGC5_TMR1_MASK (0x1000000U) macro14787 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK)
16421 #define SIM_SCGC5_TMR1_MASK (0x1000000U) macro16427 … SIM_SCGC5_TMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK)
16312 #define SIM_SCGC5_TMR1_MASK (0x1000000U) macro16318 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK)