SCG_VCCR_DIVCORE_MASK (reference) in projects: hal_nxp-3.6.0

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Searched refs:SCG_VCCR_DIVCORE_MASK (Results 1 – 25 of 27) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
D	S32K116_SCG.h	`201 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 204 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K118_SCG.h	`201 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 204 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K142W_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K144_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K144W_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K142_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K148_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	S32K146_SCG.h	`205 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 208 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
D	Clock_Ip_Divider.c	`537 RegValue &= ~SCG_VCCR_DIVCORE_MASK; in Clock_Ip_SetScgVlprDivcore_TrustedCall()`
D	Clock_Ip_Specific.c	`789 …ividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->VCCR & SCG_VCCR_DIVCORE_MASK) >> SCG_VC… in getCoreDividerConfig()`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z4/
D	MKE14Z4.h	`9817 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 9837 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z4/
D	MKE15Z4.h	`9819 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 9839 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE12Z7/
D	MKE12Z7.h	`12345 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 12365 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16Z4/
D	MKE16Z4.h	`10656 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 10676 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE13Z7/
D	MKE13Z7.h	`12348 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 12368 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE17Z7/
D	MKE17Z7.h	`12351 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 12371 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z7/
D	MKE15Z7.h	`12600 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 12620 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z7/
D	MKE14Z7.h	`12597 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 12617 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14F16/
D	MKE14F16.h	`15590 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 15610 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A31A/
D	K32L2A31A.h	`14110 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 14130 …G_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A41A/
D	K32L2A41A.h	`14110 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 14130 …G_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16F16/
D	MKE16F16.h	`16590 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 16610 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE18F16/
D	MKE18F16.h	`16596 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 16616 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/
D	K32L3A60_cm0plus.h	`15464 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 15484 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`
D	K32L3A60_cm4.h	`15414 #define SCG_VCCR_DIVCORE_MASK (0xF0000U) macro 15434 … (((uint32_t)(((uint32_t)(x)) << SCG_VCCR_DIVCORE_SHIFT)) & SCG_VCCR_DIVCORE_MASK)`

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