Searched refs:PLLDIG_PLLODIV_DIV_MASK (Results 1 – 3 of 3) sorted by relevance
204 #define PLLDIG_PLLODIV_DIV_MASK (0xFF0000U) macro207 … (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLODIV_DIV_SHIFT)) & PLLDIG_PLLODIV_DIV_MASK)
1416 …Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) +… in Clock_Ip_Get_COREPLL_PHI0_Frequency()1485 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()1494 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()1502 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()1510 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()1518 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI4_Frequency()1526 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI5_Frequency()1534 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI6_Frequency()1603 …Frequency /= (((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + … in Clock_Ip_Get_DDRPLL_PHI0_Frequency()
324 RegValue &= ~PLLDIG_PLLODIV_DIV_MASK; in Clock_Ip_SetPlldigPll0divDeDivOutput()