1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Frequency.c
8 * @version 1.0.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Clock_Ip_Private.h"
30
31 #if defined(CLOCK_IP_PLATFORM_SPECIFIC)
32
33
34 #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON))
35
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define CLOCK_IP_FREQUENCY_VENDOR_ID_C 43
41 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C 4
42 #define CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C 7
43 #define CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C 0
44 #define CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C 1
45 #define CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C 0
46 #define CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C 0
47
48 /*==================================================================================================
49 * FILE VERSION CHECKS
50 ==================================================================================================*/
51 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same vendor */
52 #if (CLOCK_IP_FREQUENCY_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
53 #error "Clock_Ip_Frequency.c and Clock_Ip_Private.h have different vendor ids"
54 #endif
55
56 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Autosar version */
57 #if ((CLOCK_IP_FREQUENCY_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
58 (CLOCK_IP_FREQUENCY_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
59 (CLOCK_IP_FREQUENCY_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
60 )
61 #error "AutoSar Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
62 #endif
63
64 /* Check if Clock_Ip_Frequency.c file and Clock_Ip_Private.h file are of the same Software version */
65 #if ((CLOCK_IP_FREQUENCY_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
66 (CLOCK_IP_FREQUENCY_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
67 (CLOCK_IP_FREQUENCY_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
68 )
69 #error "Software Version Numbers of Clock_Ip_Frequency.c and Clock_Ip_Private.h are different"
70 #endif
71 /*==================================================================================================
72 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
73 ==================================================================================================*/
74
75 typedef struct{
76
77 Clock_Ip_NameType Name;
78 uint32 Frequency;
79
80 }extSignalFreq;
81
82 /*==================================================================================================
83 * LOCAL MACROS
84 ==================================================================================================*/
85
86 #define CLOCK_IP_SELECTOR_SOURCE_NO 64U
87 #define CLOCK_IP_EXT_SIGNALS_NO 8U
88 #define CLOCK_IP_DFS_MASK_0_CHANNEL 1U
89 #define CLOCK_IP_DFS_MASK_1_CHANNEL 2U
90 #define CLOCK_IP_DFS_MASK_2_CHANNEL 4U
91 #define CLOCK_IP_DFS_MASK_3_CHANNEL 8U
92 #define CLOCK_IP_DFS_MASK_4_CHANNEL 16U
93 #define CLOCK_IP_DFS_MASK_5_CHANNEL 32U
94 #define CLOCK_IP_MUL_BY_16384 14U
95 #define CLOCK_IP_MUL_BY_2048 11U
96 #define CLOCK_IP_MUL_BY_32 5U
97 #define CLOCK_IP_MUL_BY_16 4U
98 #define CLOCK_IP_MUL_BY_4 2U
99 #define CLOCK_IP_MUL_BY_2 1U
100 #define CLOCK_IP_DISABLED 0U
101 #define CLOCK_IP_ENABLED 0xFFFFFFFFU
102
103 #define CLOCK_IP_ETH_RGMII_REF_CLK_INDEX_ENTRY 0U
104 #define CLOCK_IP_TMR_1588_CLK_INDEX_ENTRY 1U
105 #define CLOCK_IP_ETH0_EXT_RX_CLK_INDEX_ENTRY 2U
106 #define CLOCK_IP_ETH0_EXT_TX_CLK_INDEX_ENTRY 3U
107 #define CLOCK_IP_ETH1_EXT_RX_CLK_INDEX_ENTRY 4U
108 #define CLOCK_IP_ETH1_EXT_TX_CLK_INDEX_ENTRY 5U
109 #define CLOCK_IP_LFAST0_EXT_REF_CLK_INDEX_ENTRY 6U
110 #define CLOCK_IP_LFAST1_EXT_REF_CLK_INDEX_ENTRY 7U
111
112
113 #define CLOCK_IP_CLKOUT_INDEX0 0U
114 #define CLOCK_IP_CLKOUT_INDEX1 1U
115 #define CLOCK_IP_CLKOUT_INDEX2 2U
116 #define CLOCK_IP_CLKOUT_INDEX3 3U
117 #define CLOCK_IP_CLKOUT_INDEX4 4U
118 #define CLOCK_IP_CLKOUT_NO 5U
119
120
121 #define CLOCK_IP_CLKPSI5_S_UTIL_INDEX0 0U
122 #define CLOCK_IP_CLKPSI5_S_UTIL_INDEX1 1U
123 #define CLOCK_IP_CLKPSI5_S_UTIL_NO 2U
124
125
126 #define CLOCK_IP_COREPLL_FREQ 2000000000U
127 #define CLOCK_IP_COREPLL_CHECKSUM 4147U
128 #define CLOCK_IP_PERIPHPLL_FREQ 2000000000U
129 #define CLOCK_IP_PERIPHPLL_CHECKSUM 4147U
130 #define CLOCK_IP_DDRPLL_FREQ 1600000000U
131 #define CLOCK_IP_DDRPLL_CHECKSUM 4137U
132 #define CLOCK_IP_COREDFS1_FREQ 800000000U
133 #define CLOCK_IP_COREDFS1_CHECKSUM 5694U
134 #define CLOCK_IP_COREDFS2_FREQ 800000000U
135 #define CLOCK_IP_COREDFS2_CHECKSUM 5694U
136 #define CLOCK_IP_COREDFS3_FREQ 0U
137 #define CLOCK_IP_COREDFS3_CHECKSUM 5943U
138 #define CLOCK_IP_COREDFS4_FREQ 0U
139 #define CLOCK_IP_COREDFS4_CHECKSUM 5943U
140 #define CLOCK_IP_COREDFS5_FREQ 0U
141 #define CLOCK_IP_COREDFS5_CHECKSUM 5943U
142 #define CLOCK_IP_COREDFS6_FREQ 0U
143 #define CLOCK_IP_COREDFS6_CHECKSUM 5943U
144 #define CLOCK_IP_PERIPHDFS1_FREQ 800000000U
145 #define CLOCK_IP_PERIPHDFS1_CHECKSUM 5694U
146 #define CLOCK_IP_PERIPHDFS2_FREQ 631578947U
147 #define CLOCK_IP_PERIPHDFS2_CHECKSUM 5666U
148 #define CLOCK_IP_PERIPHDFS3_FREQ 0U
149 #define CLOCK_IP_PERIPHDFS3_CHECKSUM 5943U
150 #define CLOCK_IP_PERIPHDFS4_FREQ 1000000000U
151 #define CLOCK_IP_PERIPHDFS4_CHECKSUM 5687U
152 #define CLOCK_IP_PERIPHDFS5_FREQ 1000000000U
153 #define CLOCK_IP_PERIPHDFS5_CHECKSUM 5687U
154 #define CLOCK_IP_PERIPHDFS6_FREQ 1000000000U
155 #define CLOCK_IP_PERIPHDFS6_CHECKSUM 5687U
156
157 /*==================================================================================================
158 GLOBAL FUNCTION PROTOTYPES
159 ==================================================================================================*/
160
161 /*==================================================================================================
162 LOCAL FUNCTION PROTOTYPES
163 ==================================================================================================*/
164 /* Clock start section code */
165 #define MCU_START_SEC_CODE
166 #include "Mcu_MemMap.h"
167
168 static uint32 PLL_VCO(const PLLDIG_Type *Base);
169 static uint32 LFAST_PLL_VCO(const LFAST_Type *Base);
170 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin);
171 static uint32 Clock_Ip_Get_Zero_Frequency(void);
172 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void);
173 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void);
174 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void);
175 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
176 static uint32 Clock_Ip_Get_FIRC_AE_CLK_Frequency(void);
177 #endif
178 static uint32 Clock_Ip_Get_COREPLL_CLK_Frequency(void);
179 static uint32 Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void);
180 static uint32 Clock_Ip_Get_DDRPLL_CLK_Frequency(void);
181 static uint32 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void);
182 static uint32 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void);
183 static uint32 Clock_Ip_Get_COREPLL_PHI0_Frequency(void);
184 static uint32 Clock_Ip_Get_COREPLL_DFS0_Frequency(void);
185 static uint32 Clock_Ip_Get_COREPLL_DFS1_Frequency(void);
186 static uint32 Clock_Ip_Get_COREPLL_DFS2_Frequency(void);
187 static uint32 Clock_Ip_Get_COREPLL_DFS3_Frequency(void);
188 static uint32 Clock_Ip_Get_COREPLL_DFS4_Frequency(void);
189 static uint32 Clock_Ip_Get_COREPLL_DFS5_Frequency(void);
190 static uint32 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void);
191 static uint32 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void);
192 static uint32 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void);
193 static uint32 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void);
194 static uint32 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void);
195 static uint32 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void);
196 static uint32 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void);
197 static uint32 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void);
198 static uint32 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void);
199 static uint32 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void);
200 static uint32 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void);
201 static uint32 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void);
202 static uint32 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void);
203 static uint32 Clock_Ip_Get_DDRPLL_PHI0_Frequency(void);
204 static uint32 Clock_Ip_Get_eth_rgmii_ref_Frequency(void);
205 static uint32 Clock_Ip_Get_tmr_1588_ref_Frequency(void);
206 static uint32 Clock_Ip_Get_eth0_ext_rx_Frequency(void);
207 static uint32 Clock_Ip_Get_eth0_ext_tx_Frequency(void);
208 static uint32 Clock_Ip_Get_eth1_ext_rx_Frequency(void);
209 static uint32 Clock_Ip_Get_eth1_ext_tx_Frequency(void);
210 static uint32 Clock_Ip_Get_lfast0_ext_ref_Frequency(void);
211 static uint32 Clock_Ip_Get_lfast1_ext_ref_Frequency(void);
212 static uint32 Clock_Ip_Get_DDR_CLK_Frequency(void);
213 static uint32 Clock_Ip_Get_P0_SYS_CLK_Frequency(void);
214 static uint32 Clock_Ip_Get_P1_SYS_CLK_Frequency(void);
215 static uint32 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void);
216 static uint32 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void);
217 static uint32 Clock_Ip_Get_P2_SYS_CLK_Frequency(void);
218 static uint32 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void);
219 static uint32 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void);
220 static uint32 Clock_Ip_Get_P3_SYS_CLK_Frequency(void);
221 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void);
222 static uint32 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void);
223 static uint32 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void);
224 static uint32 Clock_Ip_Get_P4_SYS_CLK_Frequency(void);
225 static uint32 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void);
226 static uint32 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void);
227 static uint32 Clock_Ip_Get_P5_SYS_CLK_Frequency(void);
228 static uint32 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void);
229 static uint32 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void);
230 static uint32 Clock_Ip_Get_P2_MATH_CLK_Frequency(void);
231 static uint32 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void);
232 static uint32 Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void);
233 static uint32 Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void);
234 static uint32 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void);
235 static uint32 Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void);
236 static uint32 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void);
237 static uint32 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void);
238 static uint32 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void);
239 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
240 static uint32 Clock_Ip_Get_SYSTEM_CLK_Frequency(void);
241 #endif
242 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
243 static uint32 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void);
244 #endif
245 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK)
246 static uint32 Clock_Ip_Get_SYSTEM_DIV4_MON1_CLK_Frequency(void);
247 #endif
248 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void);
249 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void);
250 static uint32 Clock_Ip_Get_CE_EDMA_CLK_Frequency(void);
251 static uint32 Clock_Ip_Get_CE_PIT0_CLK_Frequency(void);
252 static uint32 Clock_Ip_Get_CE_PIT1_CLK_Frequency(void);
253 static uint32 Clock_Ip_Get_CE_PIT2_CLK_Frequency(void);
254 static uint32 Clock_Ip_Get_CE_PIT3_CLK_Frequency(void);
255 static uint32 Clock_Ip_Get_CE_PIT4_CLK_Frequency(void);
256 static uint32 Clock_Ip_Get_CE_PIT5_CLK_Frequency(void);
257 static uint32 Clock_Ip_Get_CTU_CLK_Frequency(void);
258 static uint32 Clock_Ip_Get_DMACRC0_CLK_Frequency(void);
259 static uint32 Clock_Ip_Get_DMACRC1_CLK_Frequency(void);
260 static uint32 Clock_Ip_Get_DMACRC4_CLK_Frequency(void);
261 static uint32 Clock_Ip_Get_DMACRC5_CLK_Frequency(void);
262 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void);
263 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void);
264 static uint32 Clock_Ip_Get_DMAMUX4_CLK_Frequency(void);
265 static uint32 Clock_Ip_Get_DMAMUX5_CLK_Frequency(void);
266 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void);
267 static uint32 Clock_Ip_Get_CLKOUT0_CLK_Frequency(void);
268 static uint32 Clock_Ip_Get_CLKOUT1_CLK_Frequency(void);
269 static uint32 Clock_Ip_Get_CLKOUT2_CLK_Frequency(void);
270 static uint32 Clock_Ip_Get_CLKOUT3_CLK_Frequency(void);
271 static uint32 Clock_Ip_Get_CLKOUT4_CLK_Frequency(void);
272 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void);
273 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void);
274 static uint32 Clock_Ip_Get_EDMA3_CLK_Frequency(void);
275 static uint32 Clock_Ip_Get_EDMA4_CLK_Frequency(void);
276 static uint32 Clock_Ip_Get_EDMA5_CLK_Frequency(void);
277 static uint32 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void);
278 static uint32 Clock_Ip_Get_ENET0_CLK_Frequency(void);
279 static uint32 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void);
280 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void);
281 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void);
282 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void);
283 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void);
284 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void);
285 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void);
286 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void);
287 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void);
288 static uint32 Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void);
289 static uint32 Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void);
290 static uint32 Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void);
291 static uint32 Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void);
292 static uint32 Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void);
293 static uint32 Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void);
294 static uint32 Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void);
295 static uint32 Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void);
296 static uint32 Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void);
297 static uint32 Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void);
298 static uint32 Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void);
299 static uint32 Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void);
300 static uint32 Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void);
301 static uint32 Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void);
302 static uint32 Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void);
303 static uint32 Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void);
304 static uint32 Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void);
305 static uint32 Clock_Ip_Get_FRAY0_CLK_Frequency(void);
306 static uint32 Clock_Ip_Get_FRAY1_CLK_Frequency(void);
307 static uint32 Clock_Ip_Get_GTM_CLK_Frequency(void);
308 static uint32 Clock_Ip_Get_IIIC0_CLK_Frequency(void);
309 static uint32 Clock_Ip_Get_IIIC1_CLK_Frequency(void);
310 static uint32 Clock_Ip_Get_IIIC2_CLK_Frequency(void);
311 static uint32 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void);
312 static uint32 Clock_Ip_Get_LIN0_CLK_Frequency(void);
313 static uint32 Clock_Ip_Get_LIN1_CLK_Frequency(void);
314 static uint32 Clock_Ip_Get_LIN2_CLK_Frequency(void);
315 static uint32 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void);
316 static uint32 Clock_Ip_Get_LIN3_CLK_Frequency(void);
317 static uint32 Clock_Ip_Get_LIN4_CLK_Frequency(void);
318 static uint32 Clock_Ip_Get_LIN5_CLK_Frequency(void);
319 static uint32 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void);
320 static uint32 Clock_Ip_Get_LIN6_CLK_Frequency(void);
321 static uint32 Clock_Ip_Get_LIN7_CLK_Frequency(void);
322 static uint32 Clock_Ip_Get_LIN8_CLK_Frequency(void);
323 static uint32 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void);
324 static uint32 Clock_Ip_Get_LIN9_CLK_Frequency(void);
325 static uint32 Clock_Ip_Get_LIN10_CLK_Frequency(void);
326 static uint32 Clock_Ip_Get_LIN11_CLK_Frequency(void);
327 static uint32 Clock_Ip_Get_MSCDSPI_CLK_Frequency(void);
328 static uint32 Clock_Ip_Get_MSCLIN_CLK_Frequency(void);
329 static uint32 Clock_Ip_Get_NANO_CLK_Frequency(void);
330 static uint32 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void);
331 static uint32 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void);
332 static uint32 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void);
333 static uint32 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void);
334 static uint32 Clock_Ip_Get_P0_GTM_CLK_Frequency(void);
335 static uint32 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void);
336 static uint32 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void);
337 static uint32 Clock_Ip_Get_P0_LIN_CLK_Frequency(void);
338 static uint32 Clock_Ip_Get_P0_NANO_CLK_Frequency(void);
339 static uint32 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void);
340 static uint32 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void);
341 static uint32 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void);
342 static uint32 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void);
343 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void);
344 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void);
345 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void);
346 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void);
347 static uint32 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void);
348 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void);
349 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void);
350 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void);
351 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void);
352 static uint32 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void);
353 static uint32 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void);
354 static uint32 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void);
355 static uint32 Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void);
356 static uint32 Clock_Ip_Get_ETH_TS_CLK_Frequency(void);
357 static uint32 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void);
358 static uint32 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void);
359 static uint32 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void);
360 static uint32 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void);
361 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void);
362 static uint32 Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency(void);
363 static uint32 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void);
364 static uint32 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void);
365 static uint32 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void);
366 static uint32 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void);
367 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void);
368 static uint32 Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency(void);
369 static uint32 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void);
370 static uint32 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void);
371 static uint32 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void);
372 static uint32 Clock_Ip_Get_P1_LIN_CLK_Frequency(void);
373 static uint32 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void);
374 static uint32 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void);
375 static uint32 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void);
376 static uint32 Clock_Ip_Get_P3_AES_CLK_Frequency(void);
377 static uint32 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void);
378 static uint32 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void);
379 static uint32 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void);
380 static uint32 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void);
381 static uint32 Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void);
382 static uint32 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void);
383 static uint32 Clock_Ip_Get_P4_LIN_CLK_Frequency(void);
384 static uint32 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void);
385 static uint32 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void);
386 static uint32 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void);
387 static uint32 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void);
388 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void);
389 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void);
390 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void);
391 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void);
392 static uint32 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void);
393 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void);
394 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void);
395 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void);
396 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void);
397 static uint32 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void);
398 static uint32 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void);
399 static uint32 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void);
400 static uint32 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void);
401 static uint32 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void);
402 static uint32 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void);
403 static uint32 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void);
404 static uint32 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void);
405 static uint32 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void);
406 static uint32 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void);
407 static uint32 Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void);
408 static uint32 Clock_Ip_Get_P5_AE_CLK_Frequency(void);
409 static uint32 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void);
410 static uint32 Clock_Ip_Get_P5_LIN_CLK_Frequency(void);
411 static uint32 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void);
412 static uint32 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void);
413 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void);
414 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void);
415 static uint32 Clock_Ip_Get_PIT4_CLK_Frequency(void);
416 static uint32 Clock_Ip_Get_PIT5_CLK_Frequency(void);
417 static uint32 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void);
418 static uint32 Clock_Ip_Get_PSI5_0_CLK_Frequency(void);
419 static uint32 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void);
420 static uint32 Clock_Ip_Get_PSI5_1_CLK_Frequency(void);
421 static uint32 Clock_Ip_Get_PSI5S_0_CLK_Frequency(void);
422 static uint32 Clock_Ip_Get_PSI5S_1_CLK_Frequency(void);
423 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void);
424 static uint32 Clock_Ip_Get_QSPI1_CLK_Frequency(void);
425 static uint32 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void);
426 static uint32 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void);
427 static uint32 Clock_Ip_Get_RXLUT_CLK_Frequency(void);
428 static uint32 Clock_Ip_Get_P4_SDHC_CLK_Frequency(void);
429 static uint32 Clock_Ip_Get_SDHC0_CLK_Frequency(void);
430 static uint32 Clock_Ip_Get_SINC_CLK_Frequency(void);
431 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void);
432 static uint32 Clock_Ip_Get_SIPI1_CLK_Frequency(void);
433 static uint32 Clock_Ip_Get_SIUL2_0_CLK_Frequency(void);
434 static uint32 Clock_Ip_Get_SIUL2_1_CLK_Frequency(void);
435 static uint32 Clock_Ip_Get_SIUL2_4_CLK_Frequency(void);
436 static uint32 Clock_Ip_Get_SIUL2_5_CLK_Frequency(void);
437 static uint32 Clock_Ip_Get_P0_DSPI_CLK_Frequency(void);
438 static uint32 Clock_Ip_Get_SPI0_CLK_Frequency(void);
439 static uint32 Clock_Ip_Get_SPI1_CLK_Frequency(void);
440 static uint32 Clock_Ip_Get_P1_DSPI_CLK_Frequency(void);
441 static uint32 Clock_Ip_Get_SPI2_CLK_Frequency(void);
442 static uint32 Clock_Ip_Get_SPI3_CLK_Frequency(void);
443 static uint32 Clock_Ip_Get_SPI4_CLK_Frequency(void);
444 static uint32 Clock_Ip_Get_P4_DSPI_CLK_Frequency(void);
445 static uint32 Clock_Ip_Get_SPI5_CLK_Frequency(void);
446 static uint32 Clock_Ip_Get_SPI6_CLK_Frequency(void);
447 static uint32 Clock_Ip_Get_SPI7_CLK_Frequency(void);
448 static uint32 Clock_Ip_Get_P5_DSPI_CLK_Frequency(void);
449 static uint32 Clock_Ip_Get_SPI8_CLK_Frequency(void);
450 static uint32 Clock_Ip_Get_SPI9_CLK_Frequency(void);
451 static uint32 Clock_Ip_Get_SRX0_CLK_Frequency(void);
452 static uint32 Clock_Ip_Get_SRX1_CLK_Frequency(void);
453 static uint32 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void);
454 static uint32 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void);
455 static uint32 Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void);
456 static uint32 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void);
457
458 /* Clock stop section code */
459 #define MCU_STOP_SEC_CODE
460 #include "Mcu_MemMap.h"
461
462 /*==================================================================================================
463 LOCAL CONSTANTS
464 ==================================================================================================*/
465
466 /* Clock start constant section data */
467 #define MCU_START_SEC_CONST_UNSPECIFIED
468 #include "Mcu_MemMap.h"
469
470 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
471 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};
472
473
474
475 typedef uint32 (*getFreqType)(void);
476
477 static const getFreqType Clock_Ip_apfFreqTableClkSrc[CLOCK_IP_SELECTOR_SOURCE_NO] = {
478 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 0 hardware value */
479 Clock_Ip_Get_Zero_Frequency, /* clock name for 1 hardware value */
480 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value */
481 Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
482 Clock_Ip_Get_Zero_Frequency, /* clock name for 4 hardware value */
483 Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
484 Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
485 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
486 Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value */
487 Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value */
488 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* clock name for 10 hardware value */
489 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* clock name for 11 hardware value */
490 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* clock name for 12 hardware value */
491 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* clock name for 13 hardware value */
492 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* clock name for 14 hardware value */
493 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* clock name for 15 hardware value */
494 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* clock name for 16 hardware value */
495 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
496 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
497 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
498 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* clock name for 20 hardware value */
499 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* clock name for 21 hardware value */
500 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* clock name for 22 hardware value */
501 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* clock name for 23 hardware value */
502 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* clock name for 24 hardware value */
503 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* clock name for 25 hardware value */
504 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* clock name for 26 hardware value */
505 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
506 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
507 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
508 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* clock name for 30 hardware value */
509 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* clock name for 31 hardware value */
510 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* clock name for 32 hardware value */
511 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* clock name for 33 hardware value */
512 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* clock name for 34 hardware value */
513 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* clock name for 35 hardware value */
514 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
515 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
516 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
517 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
518 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* clock name for 40 hardware value */
519 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
520 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
521 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
522 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
523 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
524 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
525 Clock_Ip_Get_eth_rgmii_ref_Frequency, /* clock name for 47 hardware value */
526 Clock_Ip_Get_tmr_1588_ref_Frequency, /* clock name for 48 hardware value */
527 Clock_Ip_Get_eth0_ext_rx_Frequency, /* clock name for 49 hardware value */
528 Clock_Ip_Get_eth0_ext_tx_Frequency, /* clock name for 50 hardware value */
529 Clock_Ip_Get_eth1_ext_rx_Frequency, /* clock name for 51 hardware value */
530 Clock_Ip_Get_eth1_ext_tx_Frequency, /* clock name for 52 hardware value */
531 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
532 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
533 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
534 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
535 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
536 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
537 Clock_Ip_Get_lfast0_ext_ref_Frequency, /* clock name for 59 hardware value */
538 Clock_Ip_Get_lfast1_ext_ref_Frequency, /* clock name for 60 hardware value */
539 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
540 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency, /* clock name for 62 hardware value */
541 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
542 };
543
544 static const getFreqType Clock_Ip_apfFreqTableCLKOUT0SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
545 Clock_Ip_Get_SIRC_CLK_Frequency, /* clock name for 0 hardware value SIRC_CLK */
546 Clock_Ip_Get_FIRC_CLK_Frequency, /* clock name for 1 hardware value FIRC_CLK */
547 Clock_Ip_Get_FXOSC_CLK_Frequency, /* clock name for 2 hardware value FXOSC_CLK */
548 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* clock name for 3 hardware value COREPLL_PHI0_CLK */
549 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* clock name for 4 hardware value COREDFS0_CLK */
550 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* clock name for 5 hardware value COREDFS1_CLK */
551 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* clock name for 6 hardware value COREDFS2_CLK */
552 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* clock name for 7 hardware value COREDFS3_CLK */
553 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* clock name for 8 hardware value COREDFS4_CLK */
554 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* clock name for 9 hardware value COREDFS5_CLK */
555 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* clock name for 10 hardware value PERIPHPLL_PHI0_CLK */
556 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* clock name for 11 hardware value PERIPHPLL_PHI1_CLK */
557 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* clock name for 12 hardware value PERIPHPLL_PHI2_CLK */
558 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* clock name for 13 hardware value PERIPHPLL_PHI3_CLK */
559 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* clock name for 14 hardware value PERIPHPLL_PHI4_CLK */
560 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* clock name for 15 hardware value PERIPHPLL_PHI5_CLK */
561 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* clock name for 16 hardware value PERIPHPLL_PHI6_CLK */
562 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* clock name for 17 hardware value PERIPHDFS0_CLK */
563 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* clock name for 18 hardware value PERIPHDFS1_CLK */
564 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* clock name for 19 hardware value PERIPHDFS2_CLK */
565 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* clock name for 20 hardware value PERIPHDFS3_CLK */
566 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* clock name for 21 hardware value PERIPHDFS4_CLK */
567 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* clock name for 22 hardware value PERIPHDFS5_CLK */
568 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* clock name for 23 hardware value DDRPLL_PHI0_CLK */
569 Clock_Ip_Get_P0_SYS_CLK_Frequency, /* clock name for 24 hardware value P0_SYS_CLK */
570 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency, /* clock name for 25 hardware value P0_REG_INTF_CLK */
571 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency, /* clock name for 26 hardware value P0_REG_INTF_2X_CLK */
572 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency, /* clock name for 27 hardware value P0_PSI5_1US_CLK */
573 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency, /* clock name for 28 hardware value P0_PSI5_125K_CLK */
574 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency, /* clock name for 29 hardware value P0_PSI5_189K_CLK */
575 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* clock name for 30 hardware value P0_PSI5_S_UTIL_CLK */
576 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency, /* clock name for 31 hardware value P0_PSI5_S_UART_CLK */
577 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency, /* clock name for 32 hardware value P0_PSI5_S_BAUD_CLK */
578 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency, /* clock name for 33 hardware value P0_PSI5_S_CORE_CLK */
579 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency, /* clock name for 34 hardware value P0_LIN_BAUD_CLK */
580 Clock_Ip_Get_P0_LIN_CLK_Frequency, /* clock name for 35 hardware value P0_LIN_CLK */
581 Clock_Ip_Get_P0_DSPI_CLK_Frequency, /* clock name for 36 hardware value P0_DSPI_CLK */
582 Clock_Ip_Get_P0_FR_PE_CLK_Frequency, /* clock name for 37 hardware value P0_FR_PE_CLK */
583 Clock_Ip_Get_P0_NANO_CLK_Frequency, /* clock name for 38 hardware value P0_NANO_CLK */
584 Clock_Ip_Get_P0_GTM_CLK_Frequency, /* clock name for 39 hardware value P0_GTM_CLK */
585 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency, /* clock name for 40 hardware value P0_GTM_NOC_CLK */
586 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency, /* clock name for 41 hardware value P0_GTM_TS_CLK */
587 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency, /* clock name for 42 hardware value P0_DSPI_MSC_CLK */
588 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency, /* clock name for 43 hardware value P0_CTU_PER_CLK */
589 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency, /* clock name for 44 hardware value P0_EMIOS_LCU_CLK */
590 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency, /* clock name for 45 hardware value CORE_PLL_REFCLKOUT */
591 Clock_Ip_Get_COREPLL_CLK_Frequency, /* clock name for 46 hardware value CORE_PLL_FBCLKOUT */
592 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency, /* clock name for 47 hardware value PERIPH_PLL_REFCLKOUT */
593 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* clock name for 48 hardware value PERIPH_PLL_FBCLKOUT */
594 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
595 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
596 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
597 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
598 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
599 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
600 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
601 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
602 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
603 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
604 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
605 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
606 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
607 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
608 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
609 };
610
611 static const getFreqType Clock_Ip_apfFreqTableCLKOUT1SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
612 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* clock name for 0 hardware value LFAST0_PLL_PH0_CLK */
613 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* clock name for 1 hardware value LFAST1_PLL_PH0_CLK */
614 Clock_Ip_Get_P1_SYS_CLK_Frequency, /* clock name for 2 hardware value P1_SYS_CLK */
615 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency, /* clock name for 3 hardware value P1_SYS_DIV2_CLK */
616 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency, /* clock name for 4 hardware value P1_SYS_DIV4_CLK */
617 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency, /* clock name for 5 hardware value P1_REG_INTF_CLK */
618 Clock_Ip_Get_P1_DSPI_CLK_Frequency, /* clock name for 6 hardware value P1_DSPI_CLK */
619 Clock_Ip_Get_P1_DSPI60_CLK_Frequency, /* clock name for 7 hardware value P1_DSPI60_CLK */
620 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency, /* clock name for 8 hardware value P1_LIN_BAUD_CLK */
621 Clock_Ip_Get_P1_LIN_CLK_Frequency, /* clock name for 9 hardware value P1_LIN_CLK */
622 Clock_Ip_Get_ETH_TS_CLK_Frequency, /* clock name for 10 hardware value ETH_TS_CLK */
623 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency, /* clock name for 11 hardware value ETH_TS_DIV4_CLK */
624 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency, /* clock name for 12 hardware value ETH0_TX_MII_CLK */
625 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency, /* clock name for 13 hardware value ETH0_TX_RGMII_CLK */
626 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency, /* clock name for 14 hardware value ETH0_RX_MII_CLK */
627 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency, /* clock name for 15 hardware value ETH0_RX_RGMII_CLK */
628 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency, /* clock name for 16 hardware value ETH0_REF_RMII_CLK */
629 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency, /* clock name for 17 hardware value ETH1_TX_MII_CLK */
630 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency, /* clock name for 18 hardware value ETH1_TX_RGMII_CLK */
631 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency, /* clock name for 19 hardware value ETH1_RX_MII_CLK */
632 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency, /* clock name for 20 hardware value ETH1_RX_RGMII_CLK */
633 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency, /* clock name for 21 hardware value ETH1_REF_RMII_CLK */
634 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value ETH_AXI_CLK */
635 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
636 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
637 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
638 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
639 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
640 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
641 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
642 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
643 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
644 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
645 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
646 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
647 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
648 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
649 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
650 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
651 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
652 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
653 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
654 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
655 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
656 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
657 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
658 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
659 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
660 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
661 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
662 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
663 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
664 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
665 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
666 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
667 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
668 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
669 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
670 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
671 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
672 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
673 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
674 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
675 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
676 };
677
678 static const getFreqType Clock_Ip_apfFreqTableCLKOUT2SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
679 Clock_Ip_Get_P4_SYS_CLK_Frequency, /* clock name for 0 hardware value P4_SYS_CLK */
680 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value P4_SYS_DIV2_CLK */
681 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency, /* clock name for 2 hardware value HSE_SYS_DIV2_CLK */
682 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P4_REG_INTF_CLK */
683 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency, /* clock name for 4 hardware value P4_REG_INTF_2X_CLK */
684 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency, /* clock name for 5 hardware value P4_PSI5_1US_CLK */
685 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency, /* clock name for 6 hardware value P4_PSI5_125K_CLK */
686 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency, /* clock name for 7 hardware value P4_PSI5_189K_CLK */
687 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* clock name for 8 hardware value P4_PSI5_S_UTIL_CLK */
688 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency, /* clock name for 9 hardware value P4_PSI5_S_UART_CLK */
689 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency, /* clock name for 10 hardware value P4_PSI5_S_BAUD_CLK */
690 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency, /* clock name for 11 hardware value P4_PSI5_S_CORE_CLK */
691 Clock_Ip_Get_P4_DSPI_CLK_Frequency, /* clock name for 12 hardware value P4_DSPI_CLK */
692 Clock_Ip_Get_P4_DSPI60_CLK_Frequency, /* clock name for 13 hardware value P4_DSPI60_CLK */
693 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency, /* clock name for 14 hardware value P4_QSPI0_2X_CLK */
694 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency, /* clock name for 15 hardware value P4_QSPI0_1X_CLK */
695 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency, /* clock name for 16 hardware value P4_LIN_BAUD_CLK */
696 Clock_Ip_Get_P4_LIN_CLK_Frequency, /* clock name for 17 hardware value P4_LIN_CLK */
697 Clock_Ip_Get_P4_SDHC_CLK_Frequency, /* clock name for 18 hardware value P4_SDHC_CLK */
698 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency, /* clock name for 19 hardware value P4_QSPI1_2X_CLK */
699 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency, /* clock name for 20 hardware value P4_QSPI1_1X_CLK */
700 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency, /* clock name for 21 hardware value P4_SDHC_IP_CLK */
701 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency, /* clock name for 22 hardware value P4_SDHC_IP_DIV2_CLK */
702 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency, /* clock name for 23 hardware value P4_EMIOS_LCU_CLK */
703 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
704 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
705 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
706 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
707 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
708 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
709 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
710 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
711 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
712 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
713 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
714 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
715 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
716 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
717 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
718 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
719 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
720 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
721 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
722 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
723 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
724 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
725 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
726 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
727 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
728 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
729 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
730 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
731 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
732 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
733 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
734 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
735 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
736 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
737 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
738 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
739 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
740 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
741 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
742 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
743 };
744
745 static const getFreqType Clock_Ip_apfFreqTableCLKOUT3SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
746 Clock_Ip_Get_P5_SYS_CLK_Frequency, /* clock name for 0 hardware value P5_SYS_CLK */
747 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value P5_SYS_DIV2_CLK */
748 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency, /* clock name for 2 hardware value P5_SYS_DIV4_CLK */
749 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P5_REG_INTF_CLK */
750 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency, /* clock name for 4 hardware value P5_LIN_BAUD_CLK */
751 Clock_Ip_Get_P5_LIN_CLK_Frequency, /* clock name for 5 hardware value P5_LIN_CLK */
752 Clock_Ip_Get_P5_DSPI_CLK_Frequency, /* clock name for 6 hardware value P5_DSPI_CLK */
753 Clock_Ip_Get_P5_DIPORT_CLK_Frequency, /* clock name for 7 hardware value P5_DIPORT_CLK */
754 Clock_Ip_Get_P5_AE_CLK_Frequency, /* clock name for 8 hardware value P5_AE_CLK */
755 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency, /* clock name for 9 hardware value P5_CANXL_PE_CLK */
756 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency, /* clock name for 10 hardware value P5_CANXL_CHI_CLK */
757 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
758 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
759 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
760 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
761 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
762 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
763 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
764 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
765 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
766 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
767 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
768 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
769 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
770 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
771 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
772 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
773 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
774 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
775 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
776 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
777 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
778 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
779 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
780 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
781 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
782 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
783 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
784 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
785 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
786 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
787 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
788 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
789 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
790 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
791 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
792 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
793 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
794 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
795 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
796 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
797 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
798 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
799 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
800 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
801 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
802 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
803 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
804 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
805 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
806 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
807 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
808 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
809 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
810 };
811
812 static const getFreqType Clock_Ip_apfFreqTableCLKOUT4SEL[CLOCK_IP_SELECTOR_SOURCE_NO] = {
813 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* clock name for 0 hardware value P3_SYS_CLK */
814 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* clock name for 1 hardware value CE_SYS_DIV2_CLK */
815 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* clock name for 2 hardware value CE_SYS_DIV4_CLK */
816 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency, /* clock name for 3 hardware value P3_REG_INTF_CLK */
817 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency, /* clock name for 4 hardware value P3_DBG_TS_CLK */
818 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency, /* clock name for 5 hardware value P3_CAN_PE_CLK */
819 Clock_Ip_Get_P2_SYS_CLK_Frequency, /* clock name for 6 hardware value P2_SYS_CLK */
820 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* clock name for 7 hardware value RTU0_CORE_DIV2_CLK */
821 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* clock name for 8 hardware value RTU1_CORE_DIV2_CLK */
822 Clock_Ip_Get_DDR_CLK_Frequency, /* clock name for 9 hardware value DDR_CLK */
823 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency, /* clock name for 10 hardware value P3_SYS_DIV2_NOC_CLK */
824 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
825 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
826 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
827 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
828 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
829 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
830 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
831 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
832 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
833 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
834 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
835 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
836 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
837 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
838 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
839 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
840 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
841 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
842 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
843 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
844 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
845 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
846 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
847 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
848 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
849 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
850 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
851 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
852 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
853 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
854 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
855 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
856 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
857 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
858 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
859 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
860 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
861 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
862 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
863 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
864 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
865 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
866 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
867 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
868 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
869 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
870 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
871 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
872 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
873 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
874 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
875 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
876 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
877 };
878
879 static const getFreqType Clock_Ip_apfFreqTableCLKOUT_MULTIPLEX[CLOCK_IP_CLKOUT_NO] = {
880 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency, /* clock name for 0 hardware value CLKOUT0_CLK */
881 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency, /* clock name for 1 hardware value CLKOUT1_CLK */
882 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency, /* clock name for 2 hardware value CLKOUT2_CLK */
883 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency, /* clock name for 3 hardware value CLKOUT3_CLK */
884 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency, /* clock name for 4 hardware value CLKOUT4_CLK */
885 };
886
887 static const getFreqType Clock_Ip_apfFreqTablePSI5_S_UTIL_MULTIPLEX[CLOCK_IP_CLKPSI5_S_UTIL_NO] = {
888 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* clock name for 0 hardware value P0_PSI5_S_UTIL_CLK */
889 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* clock name for 1 hardware value P4_PSI5_S_UTIL_CLK */
890 };
891
892 static const getFreqType Clock_Ip_apfFreqTable[CLOCK_IP_NAMES_NO] =
893 {
894 Clock_Ip_Get_Zero_Frequency, /* CLOCK_IS_OFF */
895 Clock_Ip_Get_FIRC_CLK_Frequency, /* FIRC_CLK clock */
896 Clock_Ip_Get_FXOSC_CLK_Frequency, /* FXOSC_CLK clock */
897 Clock_Ip_Get_SIRC_CLK_Frequency, /* SIRC_CLK clock */
898 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
899 Clock_Ip_Get_FIRC_AE_CLK_Frequency, /* FIRC_AE_CLK clock */
900 #endif
901 Clock_Ip_Get_COREPLL_CLK_Frequency, /* COREPLL_CLK clock */
902 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* PERIPHPLL_CLK clock */
903 Clock_Ip_Get_DDRPLL_CLK_Frequency, /* DDRPLL_CLK clock */
904 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* LFAST0_PLL_CLK clock */
905 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* LFAST1_PLL_CLK clock */
906 Clock_Ip_Get_COREPLL_PHI0_Frequency, /* COREPLL_PHI0 clock */
907 Clock_Ip_Get_COREPLL_DFS0_Frequency, /* COREPLL_DFS0 clock */
908 Clock_Ip_Get_COREPLL_DFS1_Frequency, /* COREPLL_DFS1 clock */
909 Clock_Ip_Get_COREPLL_DFS2_Frequency, /* COREPLL_DFS2 clock */
910 Clock_Ip_Get_COREPLL_DFS3_Frequency, /* COREPLL_DFS3 clock */
911 Clock_Ip_Get_COREPLL_DFS4_Frequency, /* COREPLL_DFS4 clock */
912 Clock_Ip_Get_COREPLL_DFS5_Frequency, /* COREPLL_DFS5 clock */
913 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency, /* PERIPHPLL_PHI0 clock */
914 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency, /* PERIPHPLL_PHI1 clock */
915 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency, /* PERIPHPLL_PHI2 clock */
916 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency, /* PERIPHPLL_PHI3 clock */
917 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency, /* PERIPHPLL_PHI4 clock */
918 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency, /* PERIPHPLL_PHI5 clock */
919 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency, /* PERIPHPLL_PHI6 clock */
920 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency, /* PERIPHPLL_DFS0 clock */
921 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency, /* PERIPHPLL_DFS1 clock */
922 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency, /* PERIPHPLL_DFS2 clock */
923 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency, /* PERIPHPLL_DFS3 clock */
924 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency, /* PERIPHPLL_DFS4 clock */
925 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency, /* PERIPHPLL_DFS5 clock */
926 Clock_Ip_Get_DDRPLL_PHI0_Frequency, /* DDRPLL_PHI0 clock */
927 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency, /* LFAST0_PLL_PH0_CLK clock */
928 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency, /* LFAST1_PLL_PH0_CLK clock */
929 Clock_Ip_Get_eth_rgmii_ref_Frequency, /* eth_rgmii_ref clock */
930 Clock_Ip_Get_tmr_1588_ref_Frequency, /* tmr_1588_ref clock */
931 Clock_Ip_Get_eth0_ext_rx_Frequency, /* eth0_ext_rx clock */
932 Clock_Ip_Get_eth0_ext_tx_Frequency, /* eth0_ext_tx clock */
933 Clock_Ip_Get_eth1_ext_rx_Frequency, /* eth1_ext_rx clock */
934 Clock_Ip_Get_eth1_ext_tx_Frequency, /* eth1_ext_tx clock */
935 Clock_Ip_Get_lfast0_ext_ref_Frequency, /* lfast0_ext_ref clock */
936 Clock_Ip_Get_lfast1_ext_ref_Frequency, /* lfast1_ext_ref clock */
937 Clock_Ip_Get_DDR_CLK_Frequency, /* DDR_CLK clock */
938 Clock_Ip_Get_P0_SYS_CLK_Frequency, /* P0_SYS_CLK clock */
939 Clock_Ip_Get_P1_SYS_CLK_Frequency, /* P1_SYS_CLK clock */
940 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency, /* P1_SYS_DIV2_CLK clock */
941 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency, /* P1_SYS_DIV4_CLK clock */
942 Clock_Ip_Get_P2_SYS_CLK_Frequency, /* P2_SYS_CLK clock */
943 Clock_Ip_Get_P2_SYS_CLK_Frequency, /* CORE_M33_CLK clock */
944 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency, /* P2_SYS_DIV2_CLK clock */
945 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency, /* P2_SYS_DIV4_CLK clock */
946 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_CLK clock */
947 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* CE_SYS_DIV2_CLK clock */
948 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* CE_SYS_DIV4_CLK clock */
949 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency, /* P3_SYS_DIV2_NOC_CLK clock */
950 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency, /* P3_SYS_DIV4_CLK clock */
951 Clock_Ip_Get_P4_SYS_CLK_Frequency, /* P4_SYS_CLK clock */
952 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* P4_SYS_DIV2_CLK clock */
953 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency, /* HSE_SYS_DIV2_CLK clock */
954 Clock_Ip_Get_P5_SYS_CLK_Frequency, /* P5_SYS_CLK clock */
955 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency, /* P5_SYS_DIV2_CLK clock */
956 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency, /* P5_SYS_DIV4_CLK clock */
957 Clock_Ip_Get_P2_MATH_CLK_Frequency, /* P2_MATH_CLK clock */
958 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency, /* P2_MATH_DIV3_CLK clock */
959 Clock_Ip_Get_GLB_LBIST_CLK_Frequency, /* GLB_LBIST_CLK clock */
960 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_CLK clock */
961 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_CLK clock */
962 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_CLK clock */
963 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_CLK clock */
964 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency, /* P0_PSI5_S_UTIL_CLK clock */
965 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency, /* P4_PSI5_S_UTIL_CLK clock */
966 #if defined(CLOCK_IP_HAS_SYSTEM_DRUN_CLK)
967 Clock_Ip_Get_SYSTEM_CLK_Frequency, /* SYSTEM_DRUN_CLK clock */
968 #endif
969 #if defined(CLOCK_IP_HAS_SYSTEM_RUN0_CLK)
970 Clock_Ip_Get_Zero_Frequency, /* SYSTEM_RUN0_CLK clock */
971 #endif
972 #if defined(CLOCK_IP_HAS_SYSTEM_SAFE_CLK)
973 Clock_Ip_Get_Zero_Frequency, /* SYSTEM_SAFE_CLK clock */
974 #endif
975 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
976 Clock_Ip_Get_SYSTEM_CLK_Frequency, /* SYSTEM_CLK clock */
977 #endif
978 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
979 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency, /* SYSTEM_DIV2_CLK clock */
980 #endif
981 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK)
982 Clock_Ip_Get_SYSTEM_DIV4_MON1_CLK_Frequency, /* SYSTEM_DIV4_MON1_CLK clock */
983 #endif
984 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK)
985 Clock_Ip_Get_SYSTEM_DIV4_MON1_CLK_Frequency, /* SYSTEM_DIV4_MON2_CLK clock */
986 #endif
987 NULL_PTR, /* THE_LAST_PRODUCER_CLK*/
988 Clock_Ip_Get_ADC0_CLK_Frequency, /* ADC0_CLK clock */
989 Clock_Ip_Get_ADC1_CLK_Frequency, /* ADC1_CLK clock */
990 Clock_Ip_Get_CE_EDMA_CLK_Frequency, /* CE_EDMA_CLK clock */
991 Clock_Ip_Get_CE_PIT0_CLK_Frequency, /* CE_PIT0_CLK clock */
992 Clock_Ip_Get_CE_PIT1_CLK_Frequency, /* CE_PIT1_CLK clock */
993 Clock_Ip_Get_CE_PIT2_CLK_Frequency, /* CE_PIT2_CLK clock */
994 Clock_Ip_Get_CE_PIT3_CLK_Frequency, /* CE_PIT3_CLK clock */
995 Clock_Ip_Get_CE_PIT4_CLK_Frequency, /* CE_PIT4_CLK clock */
996 Clock_Ip_Get_CE_PIT5_CLK_Frequency, /* CE_PIT5_CLK clock */
997 Clock_Ip_Get_CLKOUT0_CLK_Frequency, /* CLKOUT0_CLK clock */
998 Clock_Ip_Get_CLKOUT1_CLK_Frequency, /* CLKOUT1_CLK clock */
999 Clock_Ip_Get_CLKOUT2_CLK_Frequency, /* CLKOUT2_CLK clock */
1000 Clock_Ip_Get_CLKOUT3_CLK_Frequency, /* CLKOUT3_CLK clock */
1001 Clock_Ip_Get_CLKOUT4_CLK_Frequency, /* CLKOUT4_CLK clock */
1002 Clock_Ip_Get_CTU_CLK_Frequency, /* CTU_CLK clock */
1003 Clock_Ip_Get_DMACRC0_CLK_Frequency, /* DMACRC0_CLK clock */
1004 Clock_Ip_Get_DMACRC1_CLK_Frequency, /* DMACRC1_CLK clock */
1005 Clock_Ip_Get_DMACRC4_CLK_Frequency, /* DMACRC4_CLK clock */
1006 Clock_Ip_Get_DMACRC5_CLK_Frequency, /* DMACRC5_CLK clock */
1007 Clock_Ip_Get_DMAMUX0_CLK_Frequency, /* DMAMUX0_CLK clock */
1008 Clock_Ip_Get_DMAMUX1_CLK_Frequency, /* DMAMUX1_CLK clock */
1009 Clock_Ip_Get_DMAMUX4_CLK_Frequency, /* DMAMUX4_CLK clock */
1010 Clock_Ip_Get_DMAMUX5_CLK_Frequency, /* DMAMUX5_CLK clock */
1011 Clock_Ip_Get_EDMA0_CLK_Frequency, /* EDMA0_CLK clock */
1012 Clock_Ip_Get_EDMA1_CLK_Frequency, /* EDMA1_CLK clock */
1013 Clock_Ip_Get_EDMA3_CLK_Frequency, /* EDMA3_CLK clock */
1014 Clock_Ip_Get_EDMA4_CLK_Frequency, /* EDMA4_CLK clock */
1015 Clock_Ip_Get_EDMA5_CLK_Frequency, /* EDMA5_CLK clock */
1016 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency, /* ETH0_TX_MII_CLK clock */
1017 Clock_Ip_Get_ENET0_CLK_Frequency, /* ENET0_CLK clock */
1018 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency, /* P3_CAN_PE_CLK clock */
1019 Clock_Ip_Get_FLEXCAN0_CLK_Frequency, /* FLEXCAN0_CLK clock */
1020 Clock_Ip_Get_FLEXCAN1_CLK_Frequency, /* FLEXCAN1_CLK clock */
1021 Clock_Ip_Get_FLEXCAN2_CLK_Frequency, /* FLEXCAN2_CLK clock */
1022 Clock_Ip_Get_FLEXCAN3_CLK_Frequency, /* FLEXCAN3_CLK clock */
1023 Clock_Ip_Get_FLEXCAN4_CLK_Frequency, /* FLEXCAN4_CLK clock */
1024 Clock_Ip_Get_FLEXCAN5_CLK_Frequency, /* FLEXCAN5_CLK clock */
1025 Clock_Ip_Get_FLEXCAN6_CLK_Frequency, /* FLEXCAN6_CLK clock */
1026 Clock_Ip_Get_FLEXCAN7_CLK_Frequency, /* FLEXCAN7_CLK clock */
1027 Clock_Ip_Get_FLEXCAN8_CLK_Frequency, /* FLEXCAN8_CLK clock */
1028 Clock_Ip_Get_FLEXCAN9_CLK_Frequency, /* FLEXCAN9_CLK clock */
1029 Clock_Ip_Get_FLEXCAN10_CLK_Frequency, /* FLEXCAN10_CLK clock */
1030 Clock_Ip_Get_FLEXCAN11_CLK_Frequency, /* FLEXCAN11_CLK clock */
1031 Clock_Ip_Get_FLEXCAN12_CLK_Frequency, /* FLEXCAN12_CLK clock */
1032 Clock_Ip_Get_FLEXCAN13_CLK_Frequency, /* FLEXCAN13_CLK clock */
1033 Clock_Ip_Get_FLEXCAN14_CLK_Frequency, /* FLEXCAN14_CLK clock */
1034 Clock_Ip_Get_FLEXCAN15_CLK_Frequency, /* FLEXCAN15_CLK clock */
1035 Clock_Ip_Get_FLEXCAN16_CLK_Frequency, /* FLEXCAN16_CLK clock */
1036 Clock_Ip_Get_FLEXCAN17_CLK_Frequency, /* FLEXCAN17_CLK clock */
1037 Clock_Ip_Get_FLEXCAN18_CLK_Frequency, /* FLEXCAN18_CLK clock */
1038 Clock_Ip_Get_FLEXCAN19_CLK_Frequency, /* FLEXCAN19_CLK clock */
1039 Clock_Ip_Get_FLEXCAN20_CLK_Frequency, /* FLEXCAN20_CLK clock */
1040 Clock_Ip_Get_FLEXCAN21_CLK_Frequency, /* FLEXCAN21_CLK clock */
1041 Clock_Ip_Get_FLEXCAN22_CLK_Frequency, /* FLEXCAN22_CLK clock */
1042 Clock_Ip_Get_FLEXCAN23_CLK_Frequency, /* FLEXCAN23_CLK clock */
1043 Clock_Ip_Get_P0_FR_PE_CLK_Frequency, /* P0_FR_PE_CLK clock */
1044 Clock_Ip_Get_FRAY0_CLK_Frequency, /* FRAY0_CLK clock */
1045 Clock_Ip_Get_FRAY1_CLK_Frequency, /* FRAY1_CLK clock */
1046 Clock_Ip_Get_GTM_CLK_Frequency, /* GTM_CLK clock */
1047 Clock_Ip_Get_IIIC0_CLK_Frequency, /* IIIC0_CLK clock */
1048 Clock_Ip_Get_IIIC1_CLK_Frequency, /* IIIC1_CLK clock */
1049 Clock_Ip_Get_IIIC2_CLK_Frequency, /* IIIC2_CLK clock */
1050 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency, /* P0_LIN_BAUD_CLK clock */
1051 Clock_Ip_Get_LIN0_CLK_Frequency, /* LIN0_CLK clock */
1052 Clock_Ip_Get_LIN1_CLK_Frequency, /* LIN1_CLK clock */
1053 Clock_Ip_Get_LIN2_CLK_Frequency, /* LIN2_CLK clock */
1054 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency, /* P1_LIN_BAUD_CLK clock */
1055 Clock_Ip_Get_LIN3_CLK_Frequency, /* LIN3_CLK clock */
1056 Clock_Ip_Get_LIN4_CLK_Frequency, /* LIN4_CLK clock */
1057 Clock_Ip_Get_LIN5_CLK_Frequency, /* LIN5_CLK clock */
1058 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency, /* P4_LIN_BAUD_CLK clock */
1059 Clock_Ip_Get_LIN6_CLK_Frequency, /* LIN6_CLK clock */
1060 Clock_Ip_Get_LIN7_CLK_Frequency, /* LIN7_CLK clock */
1061 Clock_Ip_Get_LIN8_CLK_Frequency, /* LIN8_CLK clock */
1062 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency, /* P5_LIN_BAUD_CLK clock */
1063 Clock_Ip_Get_LIN9_CLK_Frequency, /* LIN9_CLK clock */
1064 Clock_Ip_Get_LIN10_CLK_Frequency, /* LIN10_CLK clock */
1065 Clock_Ip_Get_LIN11_CLK_Frequency, /* LIN11_CLK clock */
1066 Clock_Ip_Get_MSCDSPI_CLK_Frequency, /* MSCDSPI_CLK clock */
1067 Clock_Ip_Get_MSCLIN_CLK_Frequency, /* MSCLIN_CLK clock */
1068 Clock_Ip_Get_NANO_CLK_Frequency, /* NANO_CLK clock */
1069 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency, /* P0_CLKOUT_SRC_CLK clock */
1070 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency, /* P0_CTU_PER_CLK clock */
1071 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency, /* P0_DSPI_MSC_CLK clock */
1072 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency, /* P0_EMIOS_LCU_CLK clock */
1073 Clock_Ip_Get_P0_GTM_CLK_Frequency, /* P0_GTM_CLK clock */
1074 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency, /* P0_GTM_NOC_CLK clock */
1075 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency, /* P0_GTM_TS_CLK clock */
1076 Clock_Ip_Get_P0_LIN_CLK_Frequency, /* P0_LIN_CLK clock */
1077 Clock_Ip_Get_P0_NANO_CLK_Frequency, /* P0_NANO_CLK clock */
1078 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency, /* P0_PSI5_125K_CLK clock */
1079 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency, /* P0_PSI5_189K_CLK clock */
1080 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency, /* P0_PSI5_S_BAUD_CLK clock */
1081 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency, /* P0_PSI5_S_CORE_CLK clock */
1082 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency, /* P0_PSI5_S_TRIG0_CLK clock */
1083 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency, /* P0_PSI5_S_TRIG1_CLK clock */
1084 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency, /* P0_PSI5_S_TRIG2_CLK clock */
1085 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency, /* P0_PSI5_S_TRIG3_CLK clock */
1086 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency, /* P0_PSI5_S_UART_CLK clock */
1087 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency, /* P0_PSI5_S_WDOG0_CLK clock */
1088 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency, /* P0_PSI5_S_WDOG1_CLK clock */
1089 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency, /* P0_PSI5_S_WDOG2_CLK clock */
1090 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency, /* P0_PSI5_S_WDOG3_CLK clock */
1091 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency, /* P0_REG_INTF_2X_CLK clock */
1092 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency, /* P0_REG_INTF_CLK clock */
1093 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency, /* P1_CLKOUT_SRC_CLK clock */
1094 Clock_Ip_Get_P1_DSPI60_CLK_Frequency, /* P1_DSPI60_CLK clock */
1095 Clock_Ip_Get_ETH_TS_CLK_Frequency, /* ETH_TS_CLK clock */
1096 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency, /* ETH_TS_DIV4_CLK clock */
1097 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency, /* ETH0_REF_RMII_CLK clock */
1098 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency, /* ETH0_RX_MII_CLK clock */
1099 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency, /* ETH0_RX_RGMII_CLK clock */
1100 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency, /* ETH0_TX_RGMII_CLK clock */
1101 Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency, /* ETH0_PS_TX_CLK clock */
1102 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency, /* ETH1_REF_RMII_CLK clock */
1103 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency, /* ETH1_RX_MII_CLK clock */
1104 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency, /* ETH1_RX_RGMII_CLK clock */
1105 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency, /* ETH1_TX_MII_CLK clock */
1106 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency, /* ETH1_TX_RGMII_CLK clock */
1107 Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency, /* ETH1_PS_TX_CLK clock */
1108 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency, /* P1_LFAST0_REF_CLK clock */
1109 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency, /* P1_LFAST1_REF_CLK clock */
1110 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency, /* P1_NETC_AXI_CLK clock */
1111 Clock_Ip_Get_P1_LIN_CLK_Frequency, /* P1_LIN_CLK clock */
1112 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency, /* P1_REG_INTF_CLK clock */
1113 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency, /* P2_DBG_ATB_CLK clock */
1114 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency, /* P2_REG_INTF_CLK clock */
1115 Clock_Ip_Get_P3_AES_CLK_Frequency, /* P3_AES_CLK clock */
1116 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency, /* P3_CLKOUT_SRC_CLK clock */
1117 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency, /* P3_DBG_TS_CLK clock */
1118 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency, /* P3_REG_INTF_CLK clock */
1119 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON1_CLK clock */
1120 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON2_CLK clock */
1121 Clock_Ip_Get_P3_SYS_CLK_Frequency, /* P3_SYS_MON3_CLK clock */
1122 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency, /* P4_CLKOUT_SRC_CLK clock */
1123 Clock_Ip_Get_P4_DSPI60_CLK_Frequency, /* P4_DSPI60_CLK clock */
1124 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency, /* P4_EMIOS_LCU_CLK clock */
1125 Clock_Ip_Get_P4_LIN_CLK_Frequency, /* P4_LIN_CLK clock */
1126 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency, /* P4_PSI5_125K_CLK clock */
1127 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency, /* P4_PSI5_189K_CLK clock */
1128 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency, /* P4_PSI5_S_BAUD_CLK clock */
1129 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency, /* P4_PSI5_S_CORE_CLK clock */
1130 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency, /* P4_PSI5_S_TRIG0_CLK clock */
1131 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency, /* P4_PSI5_S_TRIG1_CLK clock */
1132 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency, /* P4_PSI5_S_TRIG2_CLK clock */
1133 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency, /* P4_PSI5_S_TRIG3_CLK clock */
1134 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency, /* P4_PSI5_S_UART_CLK clock */
1135 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency, /* P4_PSI5_S_WDOG0_CLK clock */
1136 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency, /* P4_PSI5_S_WDOG1_CLK clock */
1137 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency, /* P4_PSI5_S_WDOG2_CLK clock */
1138 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency, /* P4_PSI5_S_WDOG3_CLK clock */
1139 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency, /* P4_QSPI0_2X_CLK clock */
1140 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency, /* P4_QSPI0_1X_CLK clock */
1141 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency, /* P4_QSPI1_2X_CLK clock */
1142 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency, /* P4_QSPI1_1X_CLK clock */
1143 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency, /* P4_REG_INTF_2X_CLK clock */
1144 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency, /* P4_REG_INTF_CLK clock */
1145 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency, /* P4_SDHC_IP_CLK clock */
1146 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency, /* P4_SDHC_IP_DIV2_CLK clock */
1147 Clock_Ip_Get_P5_DIPORT_CLK_Frequency, /* P5_DIPORT_CLK clock */
1148 Clock_Ip_Get_P5_AE_CLK_Frequency, /* P5_AE_CLK clock */
1149 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency, /* P5_CANXL_PE_CLK clock */
1150 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency, /* P5_CANXL_CHI_CLK clock */
1151 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency, /* P5_CLKOUT_SRC_CLK clock */
1152 Clock_Ip_Get_P5_LIN_CLK_Frequency, /* P5_LIN_CLK clock */
1153 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency, /* P5_REG_INTF_CLK clock */
1154 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency, /* P6_REG_INTF_CLK clock */
1155 Clock_Ip_Get_PIT0_CLK_Frequency, /* PIT0_CLK clock */
1156 Clock_Ip_Get_PIT1_CLK_Frequency, /* PIT1_CLK clock */
1157 Clock_Ip_Get_PIT4_CLK_Frequency, /* PIT4_CLK clock */
1158 Clock_Ip_Get_PIT5_CLK_Frequency, /* PIT5_CLK clock */
1159 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency, /* P0_PSI5_1US_CLK clock */
1160 Clock_Ip_Get_PSI5_0_CLK_Frequency, /* PSI5_0_CLK clock */
1161 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency, /* P4_PSI5_1US_CLK clock */
1162 Clock_Ip_Get_PSI5_1_CLK_Frequency, /* PSI5_1_CLK clock */
1163 Clock_Ip_Get_PSI5S_0_CLK_Frequency, /* PSI5S_0_CLK clock */
1164 Clock_Ip_Get_PSI5S_1_CLK_Frequency, /* PSI5S_1_CLK clock */
1165 Clock_Ip_Get_QSPI0_CLK_Frequency, /* QSPI0_CLK clock */
1166 Clock_Ip_Get_QSPI1_CLK_Frequency, /* QSPI1_CLK clock */
1167 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_MON1_CLK clock */
1168 Clock_Ip_Get_RTU0_CORE_CLK_Frequency, /* RTU0_CORE_MON2_CLK clock */
1169 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON1_CLK clock */
1170 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON2_CLK clock */
1171 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency, /* RTU0_CORE_DIV2_MON3_CLK clock */
1172 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency, /* RTU0_REG_INTF_CLK clock */
1173 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_MON1_CLK clock */
1174 Clock_Ip_Get_RTU1_CORE_CLK_Frequency, /* RTU1_CORE_MON2_CLK clock */
1175 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON1_CLK clock */
1176 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON2_CLK clock */
1177 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency, /* RTU1_CORE_DIV2_MON3_CLK clock */
1178 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency, /* RTU1_REG_INTF_CLK clock */
1179 Clock_Ip_Get_P4_SDHC_CLK_Frequency, /* P4_SDHC_CLK clock */
1180 Clock_Ip_Get_RXLUT_CLK_Frequency, /* RXLUT_CLK clock */
1181 Clock_Ip_Get_SDHC0_CLK_Frequency, /* SDHC0_CLK clock */
1182 Clock_Ip_Get_SINC_CLK_Frequency, /* SINC_CLK clock */
1183 Clock_Ip_Get_SIPI0_CLK_Frequency, /* SIPI0_CLK clock */
1184 Clock_Ip_Get_SIPI1_CLK_Frequency, /* SIPI1_CLK clock */
1185 Clock_Ip_Get_SIUL2_0_CLK_Frequency, /* SIUL2_0_CLK clock */
1186 Clock_Ip_Get_SIUL2_1_CLK_Frequency, /* SIUL2_1_CLK clock */
1187 Clock_Ip_Get_SIUL2_4_CLK_Frequency, /* SIUL2_4_CLK clock */
1188 Clock_Ip_Get_SIUL2_5_CLK_Frequency, /* SIUL2_5_CLK clock */
1189 Clock_Ip_Get_P0_DSPI_CLK_Frequency, /* P0_DSPI_CLK clock */
1190 Clock_Ip_Get_SPI0_CLK_Frequency, /* SPI0_CLK clock */
1191 Clock_Ip_Get_SPI1_CLK_Frequency, /* SPI1_CLK clock */
1192 Clock_Ip_Get_P1_DSPI_CLK_Frequency, /* P1_DSPI_CLK clock */
1193 Clock_Ip_Get_SPI2_CLK_Frequency, /* SPI2_CLK clock */
1194 Clock_Ip_Get_SPI3_CLK_Frequency, /* SPI3_CLK clock */
1195 Clock_Ip_Get_SPI4_CLK_Frequency, /* SPI4_CLK clock */
1196 Clock_Ip_Get_P4_DSPI_CLK_Frequency, /* P4_DSPI_CLK clock */
1197 Clock_Ip_Get_SPI5_CLK_Frequency, /* SPI5_CLK clock */
1198 Clock_Ip_Get_SPI6_CLK_Frequency, /* SPI6_CLK clock */
1199 Clock_Ip_Get_SPI7_CLK_Frequency, /* SPI7_CLK clock */
1200 Clock_Ip_Get_P5_DSPI_CLK_Frequency, /* P5_DSPI_CLK clock */
1201 Clock_Ip_Get_SPI8_CLK_Frequency, /* SPI8_CLK clock */
1202 Clock_Ip_Get_SPI9_CLK_Frequency, /* SPI9_CLK clock */
1203 Clock_Ip_Get_SRX0_CLK_Frequency, /* SRX0_CLK clock */
1204 Clock_Ip_Get_SRX1_CLK_Frequency, /* SRX1_CLK clock */
1205 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency, /* CORE_PLL_REFCLKOUT clock */
1206 Clock_Ip_Get_COREPLL_CLK_Frequency, /* CORE_PLL_FBCLKOUT clock */
1207 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency, /* PERIPH_PLL_REFCLKOUT clock */
1208 Clock_Ip_Get_PERIPHPLL_CLK_Frequency, /* PERIPH_PLL_FBCLKOUT clock */
1209 };
1210
1211 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
1212 static const getFreqType Clock_Ip_apfFreqTableAeClkSrc[CLOCK_IP_SELECTOR_SOURCE_NO] =
1213 {
1214 Clock_Ip_Get_FIRC_AE_CLK_Frequency, /* clock name for 0 hardware value */
1215 Clock_Ip_Get_P5_AE_CLK_Frequency, /* clock name for 1 hardware value */
1216 Clock_Ip_Get_Zero_Frequency, /* clock name for 2 hardware value */
1217 Clock_Ip_Get_Zero_Frequency, /* clock name for 3 hardware value */
1218 Clock_Ip_Get_Zero_Frequency, /* clock name for 4 hardware value */
1219 Clock_Ip_Get_Zero_Frequency, /* clock name for 5 hardware value */
1220 Clock_Ip_Get_Zero_Frequency, /* clock name for 6 hardware value */
1221 Clock_Ip_Get_Zero_Frequency, /* clock name for 7 hardware value */
1222 Clock_Ip_Get_Zero_Frequency, /* clock name for 8 hardware value */
1223 Clock_Ip_Get_Zero_Frequency, /* clock name for 9 hardware value */
1224 Clock_Ip_Get_Zero_Frequency, /* clock name for 10 hardware value */
1225 Clock_Ip_Get_Zero_Frequency, /* clock name for 11 hardware value */
1226 Clock_Ip_Get_Zero_Frequency, /* clock name for 12 hardware value */
1227 Clock_Ip_Get_Zero_Frequency, /* clock name for 13 hardware value */
1228 Clock_Ip_Get_Zero_Frequency, /* clock name for 14 hardware value */
1229 Clock_Ip_Get_Zero_Frequency, /* clock name for 15 hardware value */
1230 Clock_Ip_Get_Zero_Frequency, /* clock name for 16 hardware value */
1231 Clock_Ip_Get_Zero_Frequency, /* clock name for 17 hardware value */
1232 Clock_Ip_Get_Zero_Frequency, /* clock name for 18 hardware value */
1233 Clock_Ip_Get_Zero_Frequency, /* clock name for 19 hardware value */
1234 Clock_Ip_Get_Zero_Frequency, /* clock name for 20 hardware value */
1235 Clock_Ip_Get_Zero_Frequency, /* clock name for 21 hardware value */
1236 Clock_Ip_Get_Zero_Frequency, /* clock name for 22 hardware value */
1237 Clock_Ip_Get_Zero_Frequency, /* clock name for 23 hardware value */
1238 Clock_Ip_Get_Zero_Frequency, /* clock name for 24 hardware value */
1239 Clock_Ip_Get_Zero_Frequency, /* clock name for 25 hardware value */
1240 Clock_Ip_Get_Zero_Frequency, /* clock name for 26 hardware value */
1241 Clock_Ip_Get_Zero_Frequency, /* clock name for 27 hardware value */
1242 Clock_Ip_Get_Zero_Frequency, /* clock name for 28 hardware value */
1243 Clock_Ip_Get_Zero_Frequency, /* clock name for 29 hardware value */
1244 Clock_Ip_Get_Zero_Frequency, /* clock name for 30 hardware value */
1245 Clock_Ip_Get_Zero_Frequency, /* clock name for 31 hardware value */
1246 Clock_Ip_Get_Zero_Frequency, /* clock name for 32 hardware value */
1247 Clock_Ip_Get_Zero_Frequency, /* clock name for 33 hardware value */
1248 Clock_Ip_Get_Zero_Frequency, /* clock name for 34 hardware value */
1249 Clock_Ip_Get_Zero_Frequency, /* clock name for 35 hardware value */
1250 Clock_Ip_Get_Zero_Frequency, /* clock name for 36 hardware value */
1251 Clock_Ip_Get_Zero_Frequency, /* clock name for 37 hardware value */
1252 Clock_Ip_Get_Zero_Frequency, /* clock name for 38 hardware value */
1253 Clock_Ip_Get_Zero_Frequency, /* clock name for 39 hardware value */
1254 Clock_Ip_Get_Zero_Frequency, /* clock name for 40 hardware value */
1255 Clock_Ip_Get_Zero_Frequency, /* clock name for 41 hardware value */
1256 Clock_Ip_Get_Zero_Frequency, /* clock name for 42 hardware value */
1257 Clock_Ip_Get_Zero_Frequency, /* clock name for 43 hardware value */
1258 Clock_Ip_Get_Zero_Frequency, /* clock name for 44 hardware value */
1259 Clock_Ip_Get_Zero_Frequency, /* clock name for 45 hardware value */
1260 Clock_Ip_Get_Zero_Frequency, /* clock name for 46 hardware value */
1261 Clock_Ip_Get_Zero_Frequency, /* clock name for 47 hardware value */
1262 Clock_Ip_Get_Zero_Frequency, /* clock name for 48 hardware value */
1263 Clock_Ip_Get_Zero_Frequency, /* clock name for 49 hardware value */
1264 Clock_Ip_Get_Zero_Frequency, /* clock name for 50 hardware value */
1265 Clock_Ip_Get_Zero_Frequency, /* clock name for 51 hardware value */
1266 Clock_Ip_Get_Zero_Frequency, /* clock name for 52 hardware value */
1267 Clock_Ip_Get_Zero_Frequency, /* clock name for 53 hardware value */
1268 Clock_Ip_Get_Zero_Frequency, /* clock name for 54 hardware value */
1269 Clock_Ip_Get_Zero_Frequency, /* clock name for 55 hardware value */
1270 Clock_Ip_Get_Zero_Frequency, /* clock name for 56 hardware value */
1271 Clock_Ip_Get_Zero_Frequency, /* clock name for 57 hardware value */
1272 Clock_Ip_Get_Zero_Frequency, /* clock name for 58 hardware value */
1273 Clock_Ip_Get_Zero_Frequency, /* clock name for 59 hardware value */
1274 Clock_Ip_Get_Zero_Frequency, /* clock name for 60 hardware value */
1275 Clock_Ip_Get_Zero_Frequency, /* clock name for 61 hardware value */
1276 Clock_Ip_Get_Zero_Frequency, /* clock name for 62 hardware value */
1277 Clock_Ip_Get_Zero_Frequency, /* clock name for 63 hardware value */
1278 };
1279 #endif
1280
1281 /* Clock stop constant section data */
1282 #define MCU_STOP_SEC_CONST_UNSPECIFIED
1283 #include "Mcu_MemMap.h"
1284
1285 /*==================================================================================================
1286 LOCAL VARIABLES
1287 ==================================================================================================*/
1288
1289 /*==================================================================================================
1290 GLOBAL CONSTANTS
1291 ==================================================================================================*/
1292
1293 /*==================================================================================================
1294 GLOBAL VARIABLES
1295 ==================================================================================================*/
1296
1297 /* Clock start initialized section data */
1298 #define MCU_START_SEC_VAR_INIT_UNSPECIFIED
1299 #include "Mcu_MemMap.h"
1300
1301 /* External oscillators */
1302 static uint32 Clock_Ip_u32Fxosc = CLOCK_IP_DEFAULT_FXOSC_FREQUENCY;
1303 static extSignalFreq Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_EXT_SIGNALS_NO] = {{ETH_RGMII_REF_CLK,0U},{TMR_1588_CLK,0U},{ETH0_EXT_RX_CLK,0U},{ETH0_EXT_TX_CLK,0U},{ETH1_EXT_RX_CLK,0U},{ETH1_EXT_TX_CLK,0U},{LFAST0_EXT_REF_CLK,0U},{LFAST1_EXT_REF_CLK,0U}};
1304
1305 static uint32 Clock_Ip_u32CorePllFreq = CLOCK_IP_COREPLL_FREQ;
1306 static uint32 Clock_Ip_u32CorePllChecksum = CLOCK_IP_COREPLL_CHECKSUM;
1307 static uint32 Clock_Ip_u32PeriphPllFreq = CLOCK_IP_PERIPHPLL_FREQ;
1308 static uint32 Clock_Ip_u32PeriphPllChecksum = CLOCK_IP_PERIPHPLL_CHECKSUM;
1309 static uint32 Clock_Ip_u32DdrPllFreq = CLOCK_IP_DDRPLL_FREQ;
1310 static uint32 Clock_Ip_u32DdrPllChecksum = CLOCK_IP_DDRPLL_CHECKSUM;
1311 static uint32 Clock_Ip_u32CoreDfs1Freq = CLOCK_IP_COREDFS1_FREQ;
1312 static uint32 Clock_Ip_u32CoreDfs1Checksum = CLOCK_IP_COREDFS1_CHECKSUM;
1313 static uint32 Clock_Ip_u32CoreDfs2Freq = CLOCK_IP_COREDFS2_FREQ;
1314 static uint32 Clock_Ip_u32CoreDfs2Checksum = CLOCK_IP_COREDFS2_CHECKSUM;
1315 static uint32 Clock_Ip_u32CoreDfs3Freq = CLOCK_IP_COREDFS3_FREQ;
1316 static uint32 Clock_Ip_u32CoreDfs3Checksum = CLOCK_IP_COREDFS3_CHECKSUM;
1317 static uint32 Clock_Ip_u32CoreDfs4Freq = CLOCK_IP_COREDFS4_FREQ;
1318 static uint32 Clock_Ip_u32CoreDfs4Checksum = CLOCK_IP_COREDFS4_CHECKSUM;
1319 static uint32 Clock_Ip_u32CoreDfs5Freq = CLOCK_IP_COREDFS5_FREQ;
1320 static uint32 Clock_Ip_u32CoreDfs5Checksum = CLOCK_IP_COREDFS5_CHECKSUM;
1321 static uint32 Clock_Ip_u32CoreDfs6Freq = CLOCK_IP_COREDFS6_FREQ;
1322 static uint32 Clock_Ip_u32CoreDfs6Checksum = CLOCK_IP_COREDFS6_CHECKSUM;
1323 static uint32 Clock_Ip_u32PeriphDfs1Freq = CLOCK_IP_PERIPHDFS1_FREQ;
1324 static uint32 Clock_Ip_u32PeriphDfs1Checksum = CLOCK_IP_PERIPHDFS1_CHECKSUM;
1325 static uint32 Clock_Ip_u32PeriphDfs2Freq = CLOCK_IP_PERIPHDFS2_FREQ;
1326 static uint32 Clock_Ip_u32PeriphDfs2Checksum = CLOCK_IP_PERIPHDFS2_CHECKSUM;
1327 static uint32 Clock_Ip_u32PeriphDfs3Freq = CLOCK_IP_PERIPHDFS3_FREQ;
1328 static uint32 Clock_Ip_u32PeriphDfs3Checksum = CLOCK_IP_PERIPHDFS3_CHECKSUM;
1329 static uint32 Clock_Ip_u32PeriphDfs4Freq = CLOCK_IP_PERIPHDFS4_FREQ;
1330 static uint32 Clock_Ip_u32PeriphDfs4Checksum = CLOCK_IP_PERIPHDFS4_CHECKSUM;
1331 static uint32 Clock_Ip_u32PeriphDfs5Freq = CLOCK_IP_PERIPHDFS5_FREQ;
1332 static uint32 Clock_Ip_u32PeriphDfs5Checksum = CLOCK_IP_PERIPHDFS5_CHECKSUM;
1333 static uint32 Clock_Ip_u32PeriphDfs6Freq = CLOCK_IP_PERIPHDFS6_FREQ;
1334 static uint32 Clock_Ip_u32PeriphDfsChecksum = CLOCK_IP_PERIPHDFS6_CHECKSUM;
1335
1336 static uint32 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX0;
1337 static uint32 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
1338
1339 /* Clock stop initialized section data */
1340 #define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
1341 #include "Mcu_MemMap.h"
1342
1343
1344
1345 /*==================================================================================================
1346 LOCAL FUNCTIONS
1347 ==================================================================================================*/
1348 /* Clock start section code */
1349 #define MCU_START_SEC_CODE
1350 #include "Mcu_MemMap.h"
1351
1352 /* Return zero frequency */
Clock_Ip_Get_Zero_Frequency(void)1353 static uint32 Clock_Ip_Get_Zero_Frequency(void)
1354 {
1355 return 0U;
1356 }
1357 /* Return FIRC_CLK frequency */
Clock_Ip_Get_FIRC_CLK_Frequency(void)1358 static uint32 Clock_Ip_Get_FIRC_CLK_Frequency(void) {
1359
1360 return CLOCK_IP_FIRC_FREQUENCY;
1361 }
1362 /* Return FXOSC_CLK frequency */
Clock_Ip_Get_FXOSC_CLK_Frequency(void)1363 static uint32 Clock_Ip_Get_FXOSC_CLK_Frequency(void) {
1364
1365 return Clock_Ip_u32Fxosc;
1366 }
1367 /* Return SIRC_CLK frequency */
Clock_Ip_Get_SIRC_CLK_Frequency(void)1368 static uint32 Clock_Ip_Get_SIRC_CLK_Frequency(void) {
1369
1370 return CLOCK_IP_SIRC_FREQUENCY;
1371 }
1372
1373 #if defined(CLOCK_IP_HAS_FIRC_AE_CLK)
1374 /* Return FIRC_AE_CLK frequency */
Clock_Ip_Get_FIRC_AE_CLK_Frequency(void)1375 static uint32 Clock_Ip_Get_FIRC_AE_CLK_Frequency(void){
1376
1377 return CLOCK_IP_FIRC_AE_FREQUENCY;
1378 }
1379 #endif
1380
1381 /* Return COREPLL_CLK frequency */
Clock_Ip_Get_COREPLL_CLK_Frequency(void)1382 static uint32 Clock_Ip_Get_COREPLL_CLK_Frequency(void) {
1383
1384 if (Clock_Ip_u32CorePllChecksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD))
1385 {
1386 Clock_Ip_u32CorePllChecksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD);
1387 Clock_Ip_u32CorePllFreq = PLL_VCO(IP_CORE_PLL);
1388 }
1389 return (((IP_CORE_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32CorePllFreq : 0U;
1390 }
1391 /* Return PERIPHPLL_CLK frequency */
Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void)1392 static uint32 Clock_Ip_Get_PERIPHPLL_CLK_Frequency(void) {
1393
1394 if (Clock_Ip_u32PeriphPllChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD))
1395 {
1396 Clock_Ip_u32PeriphPllChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD);
1397 Clock_Ip_u32PeriphPllFreq = PLL_VCO(IP_PERIPH_PLL);
1398 }
1399 return (((IP_PERIPH_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32PeriphPllFreq : 0U;
1400 }
1401 /* Return DDRPLL_CLK frequency */
Clock_Ip_Get_DDRPLL_CLK_Frequency(void)1402 static uint32 Clock_Ip_Get_DDRPLL_CLK_Frequency(void) {
1403
1404 if (Clock_Ip_u32DdrPllChecksum != (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD))
1405 {
1406 Clock_Ip_u32DdrPllChecksum = (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD);
1407 Clock_Ip_u32DdrPllFreq = PLL_VCO(IP_DDR_PLL);
1408 }
1409 return (((IP_DDR_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_Ip_u32DdrPllFreq : 0U;
1410 }
1411 /* Return COREPLL_PHI0 frequency */
Clock_Ip_Get_COREPLL_PHI0_Frequency(void)1412 static uint32 Clock_Ip_Get_COREPLL_PHI0_Frequency(void) {
1413
1414 uint32 Frequency = Clock_Ip_Get_COREPLL_CLK_Frequency();
1415 Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1416 Frequency /= (((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1417 return Frequency;
1418 }
1419
1420 /* Return COREPLL_DFS0 frequency */
Clock_Ip_Get_COREPLL_DFS0_Frequency(void)1421 static uint32 Clock_Ip_Get_COREPLL_DFS0_Frequency(void) {
1422
1423 if (Clock_Ip_u32CoreDfs1Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[0U]))
1424 {
1425 Clock_Ip_u32CoreDfs1Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[0U]);
1426 Clock_Ip_u32CoreDfs1Freq = DFS_OUTPUT(IP_CORE_DFS,0U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1427 }
1428 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_0_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs1Freq : 0U;
1429 }
1430 /* Return COREPLL_DFS1 frequency */
Clock_Ip_Get_COREPLL_DFS1_Frequency(void)1431 static uint32 Clock_Ip_Get_COREPLL_DFS1_Frequency(void) {
1432
1433 if (Clock_Ip_u32CoreDfs2Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[1U]))
1434 {
1435 Clock_Ip_u32CoreDfs2Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[1U]);
1436 Clock_Ip_u32CoreDfs2Freq = DFS_OUTPUT(IP_CORE_DFS,1U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1437 }
1438 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_1_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs2Freq : 0U;
1439 }
1440 /* Return COREPLL_DFS2 frequency */
Clock_Ip_Get_COREPLL_DFS2_Frequency(void)1441 static uint32 Clock_Ip_Get_COREPLL_DFS2_Frequency(void) {
1442
1443 if (Clock_Ip_u32CoreDfs3Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[2U]))
1444 {
1445 Clock_Ip_u32CoreDfs3Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[2U]);
1446 Clock_Ip_u32CoreDfs3Freq = DFS_OUTPUT(IP_CORE_DFS,2U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1447 }
1448 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_2_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs3Freq : 0U;
1449 }
1450 /* Return COREPLL_DFS3 frequency */
Clock_Ip_Get_COREPLL_DFS3_Frequency(void)1451 static uint32 Clock_Ip_Get_COREPLL_DFS3_Frequency(void) {
1452
1453 if (Clock_Ip_u32CoreDfs4Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[3U]))
1454 {
1455 Clock_Ip_u32CoreDfs4Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[3U]);
1456 Clock_Ip_u32CoreDfs4Freq = DFS_OUTPUT(IP_CORE_DFS,3U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1457 }
1458 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_3_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs4Freq : 0U;
1459 }
1460 /* Return COREPLL_DFS4 frequency */
Clock_Ip_Get_COREPLL_DFS4_Frequency(void)1461 static uint32 Clock_Ip_Get_COREPLL_DFS4_Frequency(void) {
1462
1463 if (Clock_Ip_u32CoreDfs5Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[4U]))
1464 {
1465 Clock_Ip_u32CoreDfs5Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[4U]);
1466 Clock_Ip_u32CoreDfs5Freq = DFS_OUTPUT(IP_CORE_DFS,4U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1467 }
1468 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_4_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs5Freq : 0U;
1469 }
1470 /* Return COREPLL_DFS5 frequency */
Clock_Ip_Get_COREPLL_DFS5_Frequency(void)1471 static uint32 Clock_Ip_Get_COREPLL_DFS5_Frequency(void) {
1472
1473 if (Clock_Ip_u32CoreDfs6Checksum != (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[5U]))
1474 {
1475 Clock_Ip_u32CoreDfs6Checksum = (IP_CORE_PLL->PLLCLKMUX ^ IP_CORE_PLL->PLLDV ^ IP_CORE_PLL->PLLFD ^ IP_CORE_PLL->PLLSR ^ IP_CORE_DFS->DVPORT[5U]);
1476 Clock_Ip_u32CoreDfs6Freq = DFS_OUTPUT(IP_CORE_DFS,5U,Clock_Ip_Get_COREPLL_CLK_Frequency());
1477 }
1478 return ((((IP_CORE_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_5_CHANNEL) != 0U) ? Clock_Ip_u32CoreDfs6Freq : 0U;
1479 }
1480 /* Return PERIPHPLL_PHI0 frequency */
Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void)1481 static uint32 Clock_Ip_Get_PERIPHPLL_PHI0_Frequency(void) {
1482
1483 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1484 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1485 Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1486 return Frequency;
1487 }
1488
1489 /* Return PERIPHPLL_PHI1 frequency */
Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void)1490 static uint32 Clock_Ip_Get_PERIPHPLL_PHI1_Frequency(void) {
1491
1492 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1493 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1494 Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1495 return Frequency;
1496 }
1497 /* Return PERIPHPLL_PHI2 frequency */
Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void)1498 static uint32 Clock_Ip_Get_PERIPHPLL_PHI2_Frequency(void) {
1499
1500 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1501 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1502 Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1503 return Frequency;
1504 }
1505 /* Return PERIPHPLL_PHI3 frequency */
Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void)1506 static uint32 Clock_Ip_Get_PERIPHPLL_PHI3_Frequency(void) {
1507
1508 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1509 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1510 Frequency /= (((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1511 return Frequency;
1512 }
1513 /* Return PERIPHPLL_PHI4 frequency */
Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void)1514 static uint32 Clock_Ip_Get_PERIPHPLL_PHI4_Frequency(void) {
1515
1516 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1517 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1518 Frequency /= (((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1519 return Frequency;
1520 }
1521 /* Return PERIPHPLL_PHI5 frequency */
Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void)1522 static uint32 Clock_Ip_Get_PERIPHPLL_PHI5_Frequency(void) {
1523
1524 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1525 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1526 Frequency /= (((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1527 return Frequency;
1528 }
1529 /* Return PERIPHPLL_PHI6 frequency */
Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void)1530 static uint32 Clock_Ip_Get_PERIPHPLL_PHI6_Frequency(void) {
1531
1532 uint32 Frequency = Clock_Ip_Get_PERIPHPLL_CLK_Frequency();
1533 Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1534 Frequency /= (((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1535 return Frequency;
1536 }
1537
1538 /* Return PERIPHPLL_DFS0 frequency */
Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void)1539 static uint32 Clock_Ip_Get_PERIPHPLL_DFS0_Frequency(void) {
1540
1541 if (Clock_Ip_u32PeriphDfs1Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[0U]))
1542 {
1543 Clock_Ip_u32PeriphDfs1Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[0U]);
1544 Clock_Ip_u32PeriphDfs1Freq = DFS_OUTPUT(IP_PERIPH_DFS,0U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1545 }
1546 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_0_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs1Freq : 0U;
1547 }
1548 /* Return PERIPHPLL_DFS1 frequency */
Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void)1549 static uint32 Clock_Ip_Get_PERIPHPLL_DFS1_Frequency(void) {
1550
1551 if (Clock_Ip_u32PeriphDfs2Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[1U]))
1552 {
1553 Clock_Ip_u32PeriphDfs2Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[1U]);
1554 Clock_Ip_u32PeriphDfs2Freq = DFS_OUTPUT(IP_PERIPH_DFS,1U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1555 }
1556 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_1_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs2Freq : 0U;
1557 }
1558 /* Return PERIPHPLL_DFS2 frequency */
Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void)1559 static uint32 Clock_Ip_Get_PERIPHPLL_DFS2_Frequency(void) {
1560
1561 if (Clock_Ip_u32PeriphDfs3Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[2U]))
1562 {
1563 Clock_Ip_u32PeriphDfs3Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[2U]);
1564 Clock_Ip_u32PeriphDfs3Freq = DFS_OUTPUT(IP_PERIPH_DFS,2U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1565 }
1566 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_2_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs3Freq : 0U;
1567 }
1568 /* Return PERIPHPLL_DFS3 frequency */
Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void)1569 static uint32 Clock_Ip_Get_PERIPHPLL_DFS3_Frequency(void) {
1570
1571 if (Clock_Ip_u32PeriphDfs4Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[3U]))
1572 {
1573 Clock_Ip_u32PeriphDfs4Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[3U]);
1574 Clock_Ip_u32PeriphDfs4Freq = DFS_OUTPUT(IP_PERIPH_DFS,3U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1575 }
1576 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_3_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs4Freq : 0U;
1577 }
1578 /* Return PERIPHPLL_DFS4 frequency */
Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void)1579 static uint32 Clock_Ip_Get_PERIPHPLL_DFS4_Frequency(void) {
1580
1581 if (Clock_Ip_u32PeriphDfs5Checksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[4U]))
1582 {
1583 Clock_Ip_u32PeriphDfs5Checksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[4U]);
1584 Clock_Ip_u32PeriphDfs5Freq = DFS_OUTPUT(IP_PERIPH_DFS,4U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1585 }
1586 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_4_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs5Freq : 0U;
1587 }
1588 /* Return PERIPHPLL_DFS5 frequency */
Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void)1589 static uint32 Clock_Ip_Get_PERIPHPLL_DFS5_Frequency(void) {
1590
1591 if (Clock_Ip_u32PeriphDfsChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[5U]))
1592 {
1593 Clock_Ip_u32PeriphDfsChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->PLLFD ^ IP_PERIPH_PLL->PLLSR ^ IP_PERIPH_DFS->DVPORT[5U]);
1594 Clock_Ip_u32PeriphDfs6Freq = DFS_OUTPUT(IP_PERIPH_DFS,5U,Clock_Ip_Get_PERIPHPLL_CLK_Frequency());
1595 }
1596 return ((((IP_PERIPH_DFS->PORTSR >> DFS_PORTSR_PORTSTAT_SHIFT) & DFS_PORTSR_PORTSTAT_MASK) & CLOCK_IP_DFS_MASK_5_CHANNEL) != 0U) ? Clock_Ip_u32PeriphDfs6Freq : 0U;
1597 }
1598 /* Return DDRPLL_PHI0 frequency */
Clock_Ip_Get_DDRPLL_PHI0_Frequency(void)1599 static uint32 Clock_Ip_Get_DDRPLL_PHI0_Frequency(void) {
1600
1601 uint32 Frequency = Clock_Ip_Get_DDRPLL_CLK_Frequency();
1602 Frequency &= Clock_Ip_au32EnableDivider[((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLLDIG_PLLODIV_DE_SHIFT)]; /* Divider enable/disable */
1603 Frequency /= (((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + 1U); /* Apply divider value */
1604 return Frequency;
1605 }
1606
1607 /* Return eth_rgmii_ref frequency */
Clock_Ip_Get_eth_rgmii_ref_Frequency(void)1608 static uint32 Clock_Ip_Get_eth_rgmii_ref_Frequency(void) {
1609
1610 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH_RGMII_REF_CLK_INDEX_ENTRY].Frequency;
1611 }
1612
1613 /* Return tmr_1588_ref frequency */
Clock_Ip_Get_tmr_1588_ref_Frequency(void)1614 static uint32 Clock_Ip_Get_tmr_1588_ref_Frequency(void) {
1615
1616 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_TMR_1588_CLK_INDEX_ENTRY].Frequency;
1617 }
1618
1619 /* Return eth0_ext_rx frequency */
Clock_Ip_Get_eth0_ext_rx_Frequency(void)1620 static uint32 Clock_Ip_Get_eth0_ext_rx_Frequency(void) {
1621
1622 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH0_EXT_RX_CLK_INDEX_ENTRY].Frequency;
1623 }
1624 /* Return eth0_ext_tx frequency */
Clock_Ip_Get_eth0_ext_tx_Frequency(void)1625 static uint32 Clock_Ip_Get_eth0_ext_tx_Frequency(void) {
1626
1627 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH0_EXT_TX_CLK_INDEX_ENTRY].Frequency;
1628 }
1629
1630 /* Return eth1_ext_rx frequency */
Clock_Ip_Get_eth1_ext_rx_Frequency(void)1631 static uint32 Clock_Ip_Get_eth1_ext_rx_Frequency(void) {
1632
1633 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH1_EXT_RX_CLK_INDEX_ENTRY].Frequency;
1634 }
1635 /* Return eth1_ext_tx frequency */
Clock_Ip_Get_eth1_ext_tx_Frequency(void)1636 static uint32 Clock_Ip_Get_eth1_ext_tx_Frequency(void) {
1637
1638 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_ETH1_EXT_TX_CLK_INDEX_ENTRY].Frequency;
1639 }
1640
1641 /* Return lfast0_ext_ref frequency */
Clock_Ip_Get_lfast0_ext_ref_Frequency(void)1642 static uint32 Clock_Ip_Get_lfast0_ext_ref_Frequency(void) {
1643
1644 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_LFAST0_EXT_REF_CLK_INDEX_ENTRY].Frequency;
1645 }
1646 /* Return lfast1_ext_ref frequency */
Clock_Ip_Get_lfast1_ext_ref_Frequency(void)1647 static uint32 Clock_Ip_Get_lfast1_ext_ref_Frequency(void) {
1648
1649 return Clock_Ip_axExtSignalFreqEntries[CLOCK_IP_LFAST1_EXT_REF_CLK_INDEX_ENTRY].Frequency;
1650 }
1651
1652 /* Return P0_FR_PE_CLK frequency */
Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void)1653 static uint32 Clock_Ip_Get_P0_FR_PE_CLK_Frequency(void) {
1654
1655 uint32 Frequency;
1656 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1657 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1658 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1659 return Frequency;
1660 }
1661 /* Return FRAY0_CLK frequency */
Clock_Ip_Get_FRAY0_CLK_Frequency(void)1662 static uint32 Clock_Ip_Get_FRAY0_CLK_Frequency(void) {
1663
1664 uint32 Frequency;
1665 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1666 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1667 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1668 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR0PCTL & GPR0_PCTL_FR0PCTL_PCTL_MASK) >> GPR0_PCTL_FR0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1669 return Frequency;
1670 }
1671 /* Return FRAY1_CLK frequency */
Clock_Ip_Get_FRAY1_CLK_Frequency(void)1672 static uint32 Clock_Ip_Get_FRAY1_CLK_Frequency(void) {
1673
1674 uint32 Frequency;
1675 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
1676 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1677 Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1678 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->FR1PCTL & GPR0_PCTL_FR1PCTL_PCTL_MASK) >> GPR0_PCTL_FR1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1679 return Frequency;
1680 }
1681
1682 /* Return GTM_CLK frequency */
Clock_Ip_Get_GTM_CLK_Frequency(void)1683 static uint32 Clock_Ip_Get_GTM_CLK_Frequency(void) {
1684
1685 uint32 Frequency;
1686 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1687 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1688 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1689 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_GTM_MASK) >> GPR0_PCTL_GTMNANOPCTL_PCTL_GTM_SHIFT)]; /* Apply peripheral clock gate */
1690 return Frequency;
1691 }
1692
1693 /* Return P0_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void)1694 static uint32 Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency(void) {
1695
1696 uint32 Frequency;
1697 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1698 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1699 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1700 return Frequency;
1701 }
1702 /* Return LIN0_CLK frequency */
Clock_Ip_Get_LIN0_CLK_Frequency(void)1703 static uint32 Clock_Ip_Get_LIN0_CLK_Frequency(void) {
1704
1705 uint32 Frequency;
1706 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1707 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1708 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1709 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN0PCTL & GPR0_PCTL_LIN0PCTL_PCTL_MASK) >> GPR0_PCTL_LIN0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1710 return Frequency;
1711 }
1712 /* Return LIN1_CLK frequency */
Clock_Ip_Get_LIN1_CLK_Frequency(void)1713 static uint32 Clock_Ip_Get_LIN1_CLK_Frequency(void) {
1714
1715 uint32 Frequency;
1716 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1717 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1718 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1719 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN1PCTL & GPR0_PCTL_LIN1PCTL_PCTL_MASK) >> GPR0_PCTL_LIN1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1720 return Frequency;
1721 }
1722 /* Return LIN2_CLK frequency */
Clock_Ip_Get_LIN2_CLK_Frequency(void)1723 static uint32 Clock_Ip_Get_LIN2_CLK_Frequency(void) {
1724
1725 uint32 Frequency;
1726 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1727 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1728 Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1729 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->LIN2PCTL & GPR0_PCTL_LIN2PCTL_PCTL_MASK) >> GPR0_PCTL_LIN2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1730 return Frequency;
1731 }
1732 /* Return P1_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void)1733 static uint32 Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency(void) {
1734
1735 uint32 Frequency;
1736 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1737 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1738 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1739 return Frequency;
1740 }
1741 /* Return LIN3_CLK frequency */
Clock_Ip_Get_LIN3_CLK_Frequency(void)1742 static uint32 Clock_Ip_Get_LIN3_CLK_Frequency(void) {
1743
1744 uint32 Frequency;
1745 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1746 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1747 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1748 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN3PCTL & GPR1_PCTL_LIN3PCTL_PCTL_MASK) >> GPR1_PCTL_LIN3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1749 return Frequency;
1750 }
1751 /* Return LIN4_CLK frequency */
Clock_Ip_Get_LIN4_CLK_Frequency(void)1752 static uint32 Clock_Ip_Get_LIN4_CLK_Frequency(void) {
1753
1754 uint32 Frequency;
1755 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1756 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1757 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1758 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN4PCTL & GPR1_PCTL_LIN4PCTL_PCTL_MASK) >> GPR1_PCTL_LIN4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1759 return Frequency;
1760 }
1761 /* Return LIN5_CLK frequency */
Clock_Ip_Get_LIN5_CLK_Frequency(void)1762 static uint32 Clock_Ip_Get_LIN5_CLK_Frequency(void) {
1763
1764 uint32 Frequency;
1765 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1766 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1767 Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1768 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN5PCTL & GPR1_PCTL_LIN5PCTL_PCTL_MASK) >> GPR1_PCTL_LIN5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1769 return Frequency;
1770 }
1771 /* Return LIN9_CLK frequency */
Clock_Ip_Get_LIN9_CLK_Frequency(void)1772 static uint32 Clock_Ip_Get_LIN9_CLK_Frequency(void) {
1773
1774 uint32 Frequency;
1775 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1776 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1777 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1778 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN9PCTL & GPR5_PCTL_LIN9PCTL_PCTL_MASK) >> GPR5_PCTL_LIN9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1779 return Frequency;
1780 }
1781 /* Return LIN10_CLK frequency */
Clock_Ip_Get_LIN10_CLK_Frequency(void)1782 static uint32 Clock_Ip_Get_LIN10_CLK_Frequency(void) {
1783
1784 uint32 Frequency;
1785 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1786 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1787 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1788 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN10PCTL & GPR5_PCTL_LIN10PCTL_PCTL_MASK) >> GPR5_PCTL_LIN10PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1789 return Frequency;
1790 }
1791 /* Return LIN11_CLK frequency */
Clock_Ip_Get_LIN11_CLK_Frequency(void)1792 static uint32 Clock_Ip_Get_LIN11_CLK_Frequency(void) {
1793
1794 uint32 Frequency;
1795 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1796 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1797 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1798 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->LIN11PCTL & GPR5_PCTL_LIN11PCTL_PCTL_MASK) >> GPR5_PCTL_LIN11PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1799 return Frequency;
1800 }
1801
1802 /* Return MSCDSPI_CLK frequency */
Clock_Ip_Get_MSCDSPI_CLK_Frequency(void)1803 static uint32 Clock_Ip_Get_MSCDSPI_CLK_Frequency(void) {
1804
1805 uint32 Frequency;
1806 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1807 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
1808 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCDSPIPCTL & GPR0_PCTL_MSCDSPIPCTL_PCTL_MASK) >> GPR0_PCTL_MSCDSPIPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1809 return Frequency;
1810 }
1811
1812 /* Return MSCLIN_CLK frequency */
Clock_Ip_Get_MSCLIN_CLK_Frequency(void)1813 static uint32 Clock_Ip_Get_MSCLIN_CLK_Frequency(void) {
1814
1815 uint32 Frequency;
1816 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
1817 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1818 Frequency /= ((((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
1819 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->MSCLINPCTL & GPR0_PCTL_MSCLINPCTL_PCTL_MASK) >> GPR0_PCTL_MSCLINPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1820 return Frequency;
1821 }
1822
1823 /* Return NANO_CLK frequency */
Clock_Ip_Get_NANO_CLK_Frequency(void)1824 static uint32 Clock_Ip_Get_NANO_CLK_Frequency(void) {
1825
1826 uint32 Frequency;
1827 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1828 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->GTMNANOPCTL & GPR0_PCTL_GTMNANOPCTL_PCTL_NANO_MASK) >> GPR0_PCTL_GTMNANOPCTL_PCTL_NANO_SHIFT)]; /* Apply peripheral clock gate */
1829 return Frequency;
1830 }
1831
1832 /* Return P5_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void)1833 static uint32 Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency(void) {
1834
1835 uint32 Frequency;
1836 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1837 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1838 Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1839 return Frequency;
1840 }
1841 /* Return P0_DSPI_CLK frequency */
Clock_Ip_Get_P0_DSPI_CLK_Frequency(void)1842 static uint32 Clock_Ip_Get_P0_DSPI_CLK_Frequency(void) {
1843
1844 uint32 Frequency;
1845 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1846 return Frequency;
1847 }
1848 /* Return SPI0_CLK frequency */
Clock_Ip_Get_SPI0_CLK_Frequency(void)1849 static uint32 Clock_Ip_Get_SPI0_CLK_Frequency(void) {
1850
1851 uint32 Frequency;
1852 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1853 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->DSPI0PCTL & GPR0_PCTL_DSPI0PCTL_PCTL_MASK) >> GPR0_PCTL_DSPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1854 return Frequency;
1855 }
1856
1857 /* Return SPI1_CLK frequency */
Clock_Ip_Get_SPI1_CLK_Frequency(void)1858 static uint32 Clock_Ip_Get_SPI1_CLK_Frequency(void) {
1859
1860 uint32 Frequency;
1861 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
1862 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->DSPI1PCTL & GPR0_PCTL_DSPI1PCTL_PCTL_MASK) >> GPR0_PCTL_DSPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1863 return Frequency;
1864 }
1865
1866 /* Return P0_NANO_CLK frequency */
Clock_Ip_Get_P0_NANO_CLK_Frequency(void)1867 static uint32 Clock_Ip_Get_P0_NANO_CLK_Frequency(void) {
1868
1869 uint32 Frequency;
1870 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
1871 return Frequency;
1872 }
1873 /* Return P0_PSI5_1US_CLK frequency */
Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void)1874 static uint32 Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency(void) {
1875
1876 uint32 Frequency;
1877 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1878 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1879 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1880 return Frequency;
1881 }
1882 /* Return PSI5_0_CLK frequency */
Clock_Ip_Get_PSI5_0_CLK_Frequency(void)1883 static uint32 Clock_Ip_Get_PSI5_0_CLK_Frequency(void) {
1884
1885 uint32 Frequency;
1886 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1887 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1888 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1889 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->PSI50PCTL & GPR0_PCTL_PSI50PCTL_PCTL_MASK) >> GPR0_PCTL_PSI50PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1890 return Frequency;
1891 }
1892 /* Return P0_PSI5_S_TRIG0_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void)1893 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency(void) {
1894
1895 uint32 Frequency;
1896 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
1897 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1898 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1899 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1900 return Frequency;
1901 }
1902 /* Return P0_REG_INTF_CLK frequency */
Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void)1903 static uint32 Clock_Ip_Get_P0_REG_INTF_CLK_Frequency(void) {
1904
1905 uint32 Frequency;
1906 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1907 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1908 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1909 return Frequency;
1910 }
1911 /* Return P1_DSPI_CLK frequency */
Clock_Ip_Get_P1_DSPI_CLK_Frequency(void)1912 static uint32 Clock_Ip_Get_P1_DSPI_CLK_Frequency(void) {
1913
1914 uint32 Frequency;
1915 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1916 return Frequency;
1917 }
1918 /* Return SPI2_CLK frequency */
Clock_Ip_Get_SPI2_CLK_Frequency(void)1919 static uint32 Clock_Ip_Get_SPI2_CLK_Frequency(void) {
1920
1921 uint32 Frequency;
1922 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1923 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI2PCTL & GPR1_PCTL_DSPI2PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1924 return Frequency;
1925 }
1926
1927 /* Return SPI3_CLK frequency */
Clock_Ip_Get_SPI3_CLK_Frequency(void)1928 static uint32 Clock_Ip_Get_SPI3_CLK_Frequency(void) {
1929
1930 uint32 Frequency;
1931 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1932 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI3PCTL & GPR1_PCTL_DSPI3PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1933 return Frequency;
1934 }
1935
1936 /* Return SPI4_CLK frequency */
Clock_Ip_Get_SPI4_CLK_Frequency(void)1937 static uint32 Clock_Ip_Get_SPI4_CLK_Frequency(void) {
1938
1939 uint32 Frequency;
1940 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1941 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI4PCTL & GPR1_PCTL_DSPI4PCTL_PCTL_MASK) >> GPR1_PCTL_DSPI4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1942 return Frequency;
1943 }
1944 /* Return P1_LFAST0_REF_CLK frequency */
Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void)1945 static uint32 Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(void) {
1946
1947 uint32 Frequency;
1948 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_11_CSS & MC_CGM_MUX_11_CSS_SELSTAT_MASK) >> MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)]();/* Selector value */
1949 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DE_MASK) >> MC_CGM_MUX_11_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1950 Frequency /= (((IP_MC_CGM_1->MUX_11_DC_0 & MC_CGM_MUX_11_DC_0_DIV_MASK) >> MC_CGM_MUX_11_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1951 return Frequency;
1952 }
1953 /* Return P1_REG_INTF_CLK frequency */
Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void)1954 static uint32 Clock_Ip_Get_P1_REG_INTF_CLK_Frequency(void) {
1955
1956 uint32 Frequency;
1957 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1958 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1959 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1960 return Frequency;
1961 }
1962 /* Return P2_DBG_ATB_CLK frequency */
Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void)1963 static uint32 Clock_Ip_Get_P2_DBG_ATB_CLK_Frequency(void) {
1964
1965 uint32 Frequency;
1966 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
1967 return Frequency;
1968 }
1969 /* Return P2_REG_INTF_CLK frequency */
Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void)1970 static uint32 Clock_Ip_Get_P2_REG_INTF_CLK_Frequency(void) {
1971
1972 uint32 Frequency;
1973 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
1974 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_2->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
1975 Frequency /= (((IP_MC_CGM_2->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
1976 return Frequency;
1977 }
1978 /* Return P5_DSPI_CLK frequency */
Clock_Ip_Get_P5_DSPI_CLK_Frequency(void)1979 static uint32 Clock_Ip_Get_P5_DSPI_CLK_Frequency(void) {
1980
1981 uint32 Frequency;
1982 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1983 return Frequency;
1984 }
1985 /* Return SPI8_CLK frequency */
Clock_Ip_Get_SPI8_CLK_Frequency(void)1986 static uint32 Clock_Ip_Get_SPI8_CLK_Frequency(void) {
1987
1988 uint32 Frequency;
1989 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1990 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->DSPI8PCTL & GPR5_PCTL_DSPI8PCTL_PCTL_MASK) >> GPR5_PCTL_DSPI8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
1991 return Frequency;
1992 }
1993
1994 /* Return SPI9_CLK frequency */
Clock_Ip_Get_SPI9_CLK_Frequency(void)1995 static uint32 Clock_Ip_Get_SPI9_CLK_Frequency(void) {
1996
1997 uint32 Frequency;
1998 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
1999 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->DSPI9PCTL & GPR5_PCTL_DSPI9PCTL_PCTL_MASK) >> GPR5_PCTL_DSPI9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2000 return Frequency;
2001 }
2002 /* Return P5_REG_INTF_CLK frequency */
Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void)2003 static uint32 Clock_Ip_Get_P5_REG_INTF_CLK_Frequency(void) {
2004
2005 uint32 Frequency;
2006 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2007 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2008 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2009 return Frequency;
2010 }
2011
2012 /* Return DDR_CLK frequency */
Clock_Ip_Get_DDR_CLK_Frequency(void)2013 static uint32 Clock_Ip_Get_DDR_CLK_Frequency(void) {
2014
2015 uint32 Frequency;
2016 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2017 Frequency /= (((IP_MC_CGM_6->MUX_0_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2018 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR6_PCTL->DDRPCTL & GPR6_PCTL_DDRPCTL_PCTL_MASK) >> GPR6_PCTL_DDRPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2019 return Frequency;
2020 }
2021
2022 /* Return P0_SYS_CLK frequency */
Clock_Ip_Get_P0_SYS_CLK_Frequency(void)2023 static uint32 Clock_Ip_Get_P0_SYS_CLK_Frequency(void) {
2024
2025 uint32 Frequency;
2026 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2027 return Frequency;
2028 }
2029
2030 /* Return P1_SYS_CLK frequency */
Clock_Ip_Get_P1_SYS_CLK_Frequency(void)2031 static uint32 Clock_Ip_Get_P1_SYS_CLK_Frequency(void) {
2032
2033 uint32 Frequency;
2034 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2035 return Frequency;
2036 }
2037
2038 /* Return P1_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void)2039 static uint32 Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency(void) {
2040
2041 uint32 Frequency;
2042 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2043 Frequency = Frequency >> 1U;
2044 return Frequency;
2045 }
2046
2047 /* Return P1_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void)2048 static uint32 Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency(void) {
2049
2050 uint32 Frequency;
2051 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2052 Frequency = Frequency >> 2U;
2053 return Frequency;
2054 }
2055
2056 /* Return P2_SYS_CLK frequency */
Clock_Ip_Get_P2_SYS_CLK_Frequency(void)2057 static uint32 Clock_Ip_Get_P2_SYS_CLK_Frequency(void) {
2058
2059 uint32 Frequency;
2060 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2061 return Frequency;
2062 }
2063
2064
2065 /* Return P2_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void)2066 static uint32 Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency(void) {
2067
2068 uint32 Frequency;
2069 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2070 Frequency = Frequency >> 1U;
2071 return Frequency;
2072 }
2073
2074 /* Return P2_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void)2075 static uint32 Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency(void) {
2076
2077 uint32 Frequency;
2078 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2079 Frequency = Frequency >> 2U;
2080 return Frequency;
2081 }
2082
2083 /* Return P3_SYS_CLK frequency */
Clock_Ip_Get_P3_SYS_CLK_Frequency(void)2084 static uint32 Clock_Ip_Get_P3_SYS_CLK_Frequency(void) {
2085
2086 uint32 Frequency;
2087 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2088 return Frequency;
2089 }
2090
2091 /* Return CE_SYS_DIV2_CLK frequency */
Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void)2092 static uint32 Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency(void) {
2093
2094 uint32 Frequency;
2095 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2096 Frequency = Frequency >> 1U;
2097 return Frequency;
2098 }
2099
2100 /* Return P3_SYS_DIV2_NOC_CLK frequency */
Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void)2101 static uint32 Clock_Ip_Get_P3_SYS_DIV2_NOC_CLK_Frequency(void) {
2102
2103 uint32 Frequency;
2104 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2105 Frequency = Frequency >> 1U;
2106 return Frequency;
2107 }
2108
2109 /* Return P3_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void)2110 static uint32 Clock_Ip_Get_P3_SYS_DIV4_CLK_Frequency(void) {
2111
2112 uint32 Frequency;
2113 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2114 Frequency = Frequency >> 2U;
2115 return Frequency;
2116 }
2117
2118 /* Return P4_SYS_CLK frequency */
Clock_Ip_Get_P4_SYS_CLK_Frequency(void)2119 static uint32 Clock_Ip_Get_P4_SYS_CLK_Frequency(void) {
2120
2121 uint32 Frequency;
2122 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2123 return Frequency;
2124 }
2125
2126 /* Return P4_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void)2127 static uint32 Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency(void) {
2128
2129 uint32 Frequency;
2130 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2131 Frequency = Frequency >> 1U;
2132 return Frequency;
2133 }
2134
2135 /* Return HSE_SYS_DIV2_CLK frequency */
Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void)2136 static uint32 Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency(void) {
2137
2138 uint32 Frequency;
2139 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2140 Frequency = Frequency >> 1U;
2141 return Frequency;
2142 }
2143
2144 /* Return P5_SYS_CLK frequency */
Clock_Ip_Get_P5_SYS_CLK_Frequency(void)2145 static uint32 Clock_Ip_Get_P5_SYS_CLK_Frequency(void) {
2146
2147 uint32 Frequency;
2148 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2149 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2150 return Frequency;
2151 }
2152
2153 /* Return P5_SYS_DIV2_CLK frequency */
Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void)2154 static uint32 Clock_Ip_Get_P5_SYS_DIV2_CLK_Frequency(void) {
2155
2156 uint32 Frequency;
2157 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2158 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2159 Frequency = Frequency >> 1U;
2160 return Frequency;
2161 }
2162
2163 /* Return P5_SYS_DIV4_CLK frequency */
Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void)2164 static uint32 Clock_Ip_Get_P5_SYS_DIV4_CLK_Frequency(void) {
2165
2166 uint32 Frequency;
2167 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2168 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2169 Frequency = Frequency >> 2U;
2170 return Frequency;
2171 }
2172
2173 /* Return P2_MATH_CLK frequency */
Clock_Ip_Get_P2_MATH_CLK_Frequency(void)2174 static uint32 Clock_Ip_Get_P2_MATH_CLK_Frequency(void) {
2175
2176 uint32 Frequency;
2177 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2178 return Frequency;
2179 }
2180
2181 /* Return P2_MATH_DIV3_CLK frequency */
Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void)2182 static uint32 Clock_Ip_Get_P2_MATH_DIV3_CLK_Frequency(void) {
2183
2184 uint32 Frequency;
2185 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_2->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2186 Frequency /= 3U;
2187 return Frequency;
2188 }
2189
2190 /* Return GLB_LBIST_CLK frequency */
Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void)2191 static uint32 Clock_Ip_Get_GLB_LBIST_CLK_Frequency(void) {
2192
2193 uint32 Frequency;
2194 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2195 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2196 Frequency /= (((IP_MC_CGM_0->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2197 return Frequency;
2198 }
2199
2200 /* Return RTU0_CORE_CLK frequency */
Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void)2201 static uint32 Clock_Ip_Get_RTU0_CORE_CLK_Frequency(void) {
2202
2203 uint32 Frequency;
2204 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_0_CSS & RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2205 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2206 Frequency /= (((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2207 return Frequency;
2208 }
2209
2210 /* Return RTU0_CORE_DIV2_CLK frequency */
Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void)2211 static uint32 Clock_Ip_Get_RTU0_CORE_DIV2_CLK_Frequency(void) {
2212
2213 uint32 Frequency;
2214 Frequency = Clock_Ip_Get_RTU0_CORE_CLK_Frequency();/* Selector value */
2215 Frequency = Frequency >> 1U;
2216 return Frequency;
2217 }
2218
2219 /* Return RTU1_CORE_CLK frequency */
Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void)2220 static uint32 Clock_Ip_Get_RTU1_CORE_CLK_Frequency(void) {
2221
2222 uint32 Frequency;
2223 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU1__MC_CGM->MUX_0_CSS & RTU_MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2224 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2225 Frequency /= (((IP_RTU1__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2226 return Frequency;
2227 }
2228
2229 /* Return RTU1_CORE_DIV2_CLK frequency */
Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void)2230 static uint32 Clock_Ip_Get_RTU1_CORE_DIV2_CLK_Frequency(void) {
2231
2232 uint32 Frequency;
2233 Frequency = Clock_Ip_Get_RTU1_CORE_CLK_Frequency();/* Selector value */
2234 Frequency = Frequency >> 1U;
2235 return Frequency;
2236 }
2237
2238 /* Return P0_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void)2239 static uint32 Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency(void) {
2240
2241 uint32 Frequency;
2242 if (0U == ((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT))
2243 {
2244 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2245 }
2246 else
2247 {
2248 Frequency = Clock_Ip_Get_PERIPHPLL_PHI4_Frequency();
2249 }
2250 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> MC_CGM_MUX_2_DC_3_DE_SHIFT)]; /* Divider enable/disable */
2251 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
2252 return Frequency;
2253 }
2254
2255 /* Return P4_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void)2256 static uint32 Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency(void) {
2257
2258 uint32 Frequency;
2259 if (0U == ((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT))
2260 {
2261 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2262 }
2263 else
2264 {
2265 Frequency = Clock_Ip_Get_PERIPHPLL_PHI4_Frequency();
2266 }
2267 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> MC_CGM_MUX_2_DC_3_DE_SHIFT)]; /* Divider enable/disable */
2268 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
2269 return Frequency;
2270 }
2271
2272 #if defined(CLOCK_IP_HAS_SYSTEM_CLK)
2273 /* Return SYSTEM_CLK frequency */
Clock_Ip_Get_SYSTEM_CLK_Frequency(void)2274 static uint32 Clock_Ip_Get_SYSTEM_CLK_Frequency(void) {
2275
2276 uint32 Frequency;
2277 Frequency = Clock_Ip_apfFreqTableAeClkSrc[((IP_MC_ME_AE->GS & MC_ME_AE_GS_S_SYSCLK_MASK) >> MC_ME_AE_GS_S_SYSCLK_SHIFT)]();/* Selector value */
2278 return Frequency;
2279 }
2280 #endif
2281
2282 #if defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK)
2283 /* Return SYSTEM_DIV2_CLK frequency */
Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void)2284 static uint32 Clock_Ip_Get_SYSTEM_DIV2_CLK_Frequency(void)
2285 {
2286 return Clock_Ip_Get_SYSTEM_CLK_Frequency() >> 1U;
2287 }
2288 #endif
2289
2290 #if defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK)
2291 /* Return SYSTEM_DIV4_MON1_CLK frequency */
Clock_Ip_Get_SYSTEM_DIV4_MON1_CLK_Frequency(void)2292 static uint32 Clock_Ip_Get_SYSTEM_DIV4_MON1_CLK_Frequency(void)
2293 {
2294 return Clock_Ip_Get_SYSTEM_CLK_Frequency() >> 2U;
2295 }
2296 #endif
2297
2298
2299 /* Return ADC0_CLK frequency */
Clock_Ip_Get_ADC0_CLK_Frequency(void)2300 static uint32 Clock_Ip_Get_ADC0_CLK_Frequency(void) {
2301
2302 uint32 Frequency;
2303 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2304 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->ADC0PCTL & GPR0_PCTL_ADC0PCTL_PCTL_MASK) >> GPR0_PCTL_ADC0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2305 return Frequency;
2306 }
2307
2308 /* Return ADC1_CLK frequency */
Clock_Ip_Get_ADC1_CLK_Frequency(void)2309 static uint32 Clock_Ip_Get_ADC1_CLK_Frequency(void) {
2310
2311 uint32 Frequency;
2312 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2313 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->ADC1PCTL & GPR0_PCTL_ADC1PCTL_PCTL_MASK) >> GPR0_PCTL_ADC1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2314 return Frequency;
2315 }
2316
2317 /* Return CE_PIT0_CLK frequency */
Clock_Ip_Get_CE_PIT0_CLK_Frequency(void)2318 static uint32 Clock_Ip_Get_CE_PIT0_CLK_Frequency(void) {
2319
2320 uint32 Frequency;
2321 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2322 Frequency = Frequency >> 2U;
2323 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT0PCTL & GPR3_PCTL_PIT0PCTL_PCTL_MASK) >> GPR3_PCTL_PIT0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2324 return Frequency;
2325 }
2326
2327 /* Return CE_PIT1_CLK frequency */
Clock_Ip_Get_CE_PIT1_CLK_Frequency(void)2328 static uint32 Clock_Ip_Get_CE_PIT1_CLK_Frequency(void) {
2329
2330 uint32 Frequency;
2331 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2332 Frequency = Frequency >> 2U;
2333 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT1PCTL & GPR3_PCTL_PIT1PCTL_PCTL_MASK) >> GPR3_PCTL_PIT1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2334 return Frequency;
2335 }
2336
2337 /* Return CE_PIT2_CLK frequency */
Clock_Ip_Get_CE_PIT2_CLK_Frequency(void)2338 static uint32 Clock_Ip_Get_CE_PIT2_CLK_Frequency(void) {
2339
2340 uint32 Frequency;
2341 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2342 Frequency = Frequency >> 2U;
2343 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT2PCTL & GPR3_PCTL_PIT2PCTL_PCTL_MASK) >> GPR3_PCTL_PIT2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2344 return Frequency;
2345 }
2346
2347 /* Return CE_PIT3_CLK frequency */
Clock_Ip_Get_CE_PIT3_CLK_Frequency(void)2348 static uint32 Clock_Ip_Get_CE_PIT3_CLK_Frequency(void) {
2349
2350 uint32 Frequency;
2351 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2352 Frequency = Frequency >> 2U;
2353 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT3PCTL & GPR3_PCTL_PIT3PCTL_PCTL_MASK) >> GPR3_PCTL_PIT3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2354 return Frequency;
2355 }
2356
2357 /* Return CE_PIT4_CLK frequency */
Clock_Ip_Get_CE_PIT4_CLK_Frequency(void)2358 static uint32 Clock_Ip_Get_CE_PIT4_CLK_Frequency(void) {
2359
2360 uint32 Frequency;
2361 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2362 Frequency = Frequency >> 2U;
2363 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT4PCTL & GPR3_PCTL_PIT4PCTL_PCTL_MASK) >> GPR3_PCTL_PIT4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2364 return Frequency;
2365 }
2366
2367 /* Return CE_PIT5_CLK frequency */
Clock_Ip_Get_CE_PIT5_CLK_Frequency(void)2368 static uint32 Clock_Ip_Get_CE_PIT5_CLK_Frequency(void) {
2369
2370 uint32 Frequency;
2371 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2372 Frequency = Frequency >> 2U;
2373 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->PIT5PCTL & GPR3_PCTL_PIT5PCTL_PCTL_MASK) >> GPR3_PCTL_PIT5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2374 return Frequency;
2375 }
2376
2377 /* Return CTU_CLK frequency */
Clock_Ip_Get_CTU_CLK_Frequency(void)2378 static uint32 Clock_Ip_Get_CTU_CLK_Frequency(void) {
2379
2380 uint32 Frequency;
2381 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2382 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2383 Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2384 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->CTUPCTL & GPR0_PCTL_CTUPCTL_PCTL_MASK) >> GPR0_PCTL_CTUPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2385 return Frequency;
2386 }
2387
2388 /* Return DMACRC0_CLK frequency */
Clock_Ip_Get_DMACRC0_CLK_Frequency(void)2389 static uint32 Clock_Ip_Get_DMACRC0_CLK_Frequency(void) {
2390
2391 uint32 Frequency;
2392 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2393 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_1_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2394 return Frequency;
2395 }
2396
2397 /* Return DMACRC1_CLK frequency */
Clock_Ip_Get_DMACRC1_CLK_Frequency(void)2398 static uint32 Clock_Ip_Get_DMACRC1_CLK_Frequency(void) {
2399
2400 uint32 Frequency;
2401 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2402 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_1_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2403 return Frequency;
2404 }
2405
2406 /* Return DMACRC4_CLK frequency */
Clock_Ip_Get_DMACRC4_CLK_Frequency(void)2407 static uint32 Clock_Ip_Get_DMACRC4_CLK_Frequency(void) {
2408
2409 uint32 Frequency;
2410 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2411 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_1_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2412 return Frequency;
2413 }
2414
2415 /* Return DMACRC5_CLK frequency */
Clock_Ip_Get_DMACRC5_CLK_Frequency(void)2416 static uint32 Clock_Ip_Get_DMACRC5_CLK_Frequency(void) {
2417
2418 uint32 Frequency;
2419 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2420 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2421 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_1_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_1_SHIFT)]; /* Apply peripheral clock gate */
2422 return Frequency;
2423 }
2424
2425 /* Return DMAMUX0_CLK frequency */
Clock_Ip_Get_DMAMUX0_CLK_Frequency(void)2426 static uint32 Clock_Ip_Get_DMAMUX0_CLK_Frequency(void) {
2427
2428 uint32 Frequency;
2429 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2430 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2431 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2432 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_2_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2433 return Frequency;
2434 }
2435
2436 /* Return DMAMUX1_CLK frequency */
Clock_Ip_Get_DMAMUX1_CLK_Frequency(void)2437 static uint32 Clock_Ip_Get_DMAMUX1_CLK_Frequency(void) {
2438
2439 uint32 Frequency;
2440 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2441 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2442 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2443 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_2_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2444 return Frequency;
2445 }
2446
2447 /* Return DMAMUX4_CLK frequency */
Clock_Ip_Get_DMAMUX4_CLK_Frequency(void)2448 static uint32 Clock_Ip_Get_DMAMUX4_CLK_Frequency(void) {
2449
2450 uint32 Frequency;
2451 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2452 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2453 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */ Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_2_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2454 return Frequency;
2455 }
2456
2457 /* Return DMAMUX5_CLK frequency */
Clock_Ip_Get_DMAMUX5_CLK_Frequency(void)2458 static uint32 Clock_Ip_Get_DMAMUX5_CLK_Frequency(void) {
2459
2460 uint32 Frequency;
2461 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2462 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2463 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2464 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_2_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_2_SHIFT)]; /* Apply peripheral clock gate */
2465 return Frequency;
2466 }
2467
2468 /* Return CLKOUT0_CLK frequency */
Clock_Ip_Get_CLKOUT0_CLK_Frequency(void)2469 static uint32 Clock_Ip_Get_CLKOUT0_CLK_Frequency(void) {
2470
2471 uint32 Frequency;
2472 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX0;
2473 if (0U == ((IP_MC_CGM_0->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT))
2474 {
2475 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2476 }
2477 else
2478 {
2479 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2480 }
2481 Frequency /= (((IP_MC_CGM_0->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2482 return Frequency;
2483 }
2484
2485 /* Return CLKOUT1_CLK frequency */
Clock_Ip_Get_CLKOUT1_CLK_Frequency(void)2486 static uint32 Clock_Ip_Get_CLKOUT1_CLK_Frequency(void) {
2487
2488 uint32 Frequency;
2489 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX1;
2490 if (0U == ((IP_MC_CGM_1->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT))
2491 {
2492 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2493 }
2494 else
2495 {
2496 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2497 }
2498 Frequency /= (((IP_MC_CGM_1->MUX_10_DC_0 & MC_CGM_MUX_10_DC_0_DIV_MASK) >> MC_CGM_MUX_10_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2499 return Frequency;
2500 }
2501
2502 /* Return CLKOUT2_CLK frequency */
Clock_Ip_Get_CLKOUT2_CLK_Frequency(void)2503 static uint32 Clock_Ip_Get_CLKOUT2_CLK_Frequency(void) {
2504
2505 uint32 Frequency;
2506 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX2;
2507 if (0U == ((IP_MC_CGM_4->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT))
2508 {
2509 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2510 }
2511 else
2512 {
2513 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2514 }
2515 Frequency /= (((IP_MC_CGM_4->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2516 return Frequency;
2517 }
2518
2519 /* Return CLKOUT3_CLK frequency */
Clock_Ip_Get_CLKOUT3_CLK_Frequency(void)2520 static uint32 Clock_Ip_Get_CLKOUT3_CLK_Frequency(void) {
2521
2522 uint32 Frequency;
2523 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX3;
2524 if (0U == ((IP_MC_CGM_5->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT))
2525 {
2526 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2527 }
2528 else
2529 {
2530 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2531 }
2532 Frequency /= (((IP_MC_CGM_5->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2533 return Frequency;
2534 }
2535
2536 /* Return CLKOUT4_CLK frequency */
Clock_Ip_Get_CLKOUT4_CLK_Frequency(void)2537 static uint32 Clock_Ip_Get_CLKOUT4_CLK_Frequency(void) {
2538
2539 uint32 Frequency;
2540 Clock_Ip_u32ClkoutIndex = CLOCK_IP_CLKOUT_INDEX4;
2541 if (0U == ((IP_MC_CGM_3->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT))
2542 {
2543 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
2544 }
2545 else
2546 {
2547 Frequency = Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency();
2548 }
2549 Frequency /= (((IP_MC_CGM_3->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2550 return Frequency;
2551 }
2552
2553 /* Return EDMA_CLK frequency */
Clock_Ip_Get_CE_EDMA_CLK_Frequency(void)2554 static uint32 Clock_Ip_Get_CE_EDMA_CLK_Frequency(void) {
2555
2556 uint32 Frequency;
2557 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2558 Frequency = Frequency >> 1U;
2559 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->EDMACEPCTL & GPR3_PCTL_EDMACEPCTL_PCTL_MASK) >> GPR3_PCTL_EDMACEPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2560 return Frequency;
2561 }
2562
2563 /* Return EDMA0_CLK frequency */
Clock_Ip_Get_EDMA0_CLK_Frequency(void)2564 static uint32 Clock_Ip_Get_EDMA0_CLK_Frequency(void) {
2565
2566 uint32 Frequency;
2567 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2568 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_0_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2569 return Frequency;
2570 }
2571
2572 /* Return EDMA1_CLK frequency */
Clock_Ip_Get_EDMA1_CLK_Frequency(void)2573 static uint32 Clock_Ip_Get_EDMA1_CLK_Frequency(void) {
2574
2575 uint32 Frequency;
2576 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2577 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_0_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2578 return Frequency;
2579 }
2580
2581 /* Return EDMA3_CLK frequency */
Clock_Ip_Get_EDMA3_CLK_Frequency(void)2582 static uint32 Clock_Ip_Get_EDMA3_CLK_Frequency(void) {
2583
2584 uint32 Frequency;
2585 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2586 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->EDMA3PCTL & GPR3_PCTL_EDMA3PCTL_PCTL_MASK) >> GPR3_PCTL_EDMA3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2587 return Frequency;
2588 }
2589
2590 /* Return EDMA4_CLK frequency */
Clock_Ip_Get_EDMA4_CLK_Frequency(void)2591 static uint32 Clock_Ip_Get_EDMA4_CLK_Frequency(void) {
2592
2593 uint32 Frequency;
2594 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2595 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_0_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2596 return Frequency;
2597 }
2598
2599 /* Return EDMA5_CLK frequency */
Clock_Ip_Get_EDMA5_CLK_Frequency(void)2600 static uint32 Clock_Ip_Get_EDMA5_CLK_Frequency(void) {
2601
2602 uint32 Frequency;
2603 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
2604 Frequency /= (((IP_MC_CGM_5->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DIV_MASK) >> MC_CGM_MUX_0_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2605 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_0_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_0_SHIFT)]; /* Apply peripheral clock gate */
2606 return Frequency;
2607 }
2608
2609 /* Return ETH0_TX_MII_CLK frequency */
Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void)2610 static uint32 Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency(void) {
2611
2612 uint32 Frequency;
2613 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
2614 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC_CGM_MUX_6_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2615 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2616 return Frequency;
2617 }
2618
2619 /* Return ENET0_CLK frequency */
Clock_Ip_Get_ENET0_CLK_Frequency(void)2620 static uint32 Clock_Ip_Get_ENET0_CLK_Frequency(void) {
2621
2622 uint32 Frequency;
2623 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
2624 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->ENET0PCTL & GPR1_PCTL_ENET0PCTL_PCTL_MASK) >> GPR1_PCTL_ENET0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2625 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2626 return Frequency;
2627 }
2628
2629 /* Return P3_CAN_PE_CLK frequency */
Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void)2630 static uint32 Clock_Ip_Get_P3_CAN_PE_CLK_Frequency(void) {
2631
2632 uint32 Frequency;
2633 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2634 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2635 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2636 return Frequency;
2637 }
2638
2639 /* Return FLEXCAN0_CLK frequency */
Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void)2640 static uint32 Clock_Ip_Get_FLEXCAN0_CLK_Frequency(void) {
2641
2642 uint32 Frequency;
2643 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2644 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN0PCTL & GPR3_PCTL_CAN0PCTL_PCTL_MASK) >> GPR3_PCTL_CAN0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2645 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2646 return Frequency;
2647 }
2648
2649 /* Return FLEXCAN1_CLK frequency */
Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void)2650 static uint32 Clock_Ip_Get_FLEXCAN1_CLK_Frequency(void) {
2651
2652 uint32 Frequency;
2653 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2654 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN1PCTL & GPR3_PCTL_CAN1PCTL_PCTL_MASK) >> GPR3_PCTL_CAN1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2655 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2656 return Frequency;
2657 }
2658
2659 /* Return FLEXCAN2_CLK frequency */
Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void)2660 static uint32 Clock_Ip_Get_FLEXCAN2_CLK_Frequency(void) {
2661
2662 uint32 Frequency;
2663 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2664 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN2PCTL & GPR3_PCTL_CAN2PCTL_PCTL_MASK) >> GPR3_PCTL_CAN2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2665 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2666 return Frequency;
2667 }
2668
2669 /* Return FLEXCAN3_CLK frequency */
Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void)2670 static uint32 Clock_Ip_Get_FLEXCAN3_CLK_Frequency(void) {
2671
2672 uint32 Frequency;
2673 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2674 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN3PCTL & GPR3_PCTL_CAN3PCTL_PCTL_MASK) >> GPR3_PCTL_CAN3PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2675 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2676 return Frequency;
2677 }
2678
2679 /* Return FLEXCAN4_CLK frequency */
Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void)2680 static uint32 Clock_Ip_Get_FLEXCAN4_CLK_Frequency(void) {
2681
2682 uint32 Frequency;
2683 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2684 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN4PCTL & GPR3_PCTL_CAN4PCTL_PCTL_MASK) >> GPR3_PCTL_CAN4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2685 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2686 return Frequency;
2687 }
2688
2689 /* Return FLEXCAN5_CLK frequency */
Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void)2690 static uint32 Clock_Ip_Get_FLEXCAN5_CLK_Frequency(void) {
2691
2692 uint32 Frequency;
2693 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2694 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN5PCTL & GPR3_PCTL_CAN5PCTL_PCTL_MASK) >> GPR3_PCTL_CAN5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2695 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2696 return Frequency;
2697 }
2698
2699 /* Return FLEXCAN6_CLK frequency */
Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void)2700 static uint32 Clock_Ip_Get_FLEXCAN6_CLK_Frequency(void) {
2701
2702 uint32 Frequency;
2703 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2704 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN6PCTL & GPR3_PCTL_CAN6PCTL_PCTL_MASK) >> GPR3_PCTL_CAN6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2705 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2706 return Frequency;
2707 }
2708
2709 /* Return FLEXCAN7_CLK frequency */
Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void)2710 static uint32 Clock_Ip_Get_FLEXCAN7_CLK_Frequency(void) {
2711
2712 uint32 Frequency;
2713 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2714 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN7PCTL & GPR3_PCTL_CAN7PCTL_PCTL_MASK) >> GPR3_PCTL_CAN7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2715 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2716 return Frequency;
2717 }
2718
2719 /* Return FLEXCAN8_CLK frequency */
Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void)2720 static uint32 Clock_Ip_Get_FLEXCAN8_CLK_Frequency(void) {
2721
2722 uint32 Frequency;
2723 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2724 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN8PCTL & GPR3_PCTL_CAN8PCTL_PCTL_MASK) >> GPR3_PCTL_CAN8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2725 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2726 return Frequency;
2727 }
2728
2729 /* Return FLEXCAN9_CLK frequency */
Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void)2730 static uint32 Clock_Ip_Get_FLEXCAN9_CLK_Frequency(void) {
2731
2732 uint32 Frequency;
2733 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2734 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN9PCTL & GPR3_PCTL_CAN9PCTL_PCTL_MASK) >> GPR3_PCTL_CAN9PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2735 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2736 return Frequency;
2737 }
2738
2739 /* Return FLEXCAN10_CLK frequency */
Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void)2740 static uint32 Clock_Ip_Get_FLEXCAN10_CLK_Frequency(void) {
2741
2742 uint32 Frequency;
2743 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2744 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN10PCTL & GPR3_PCTL_CAN10PCTL_PCTL_MASK) >> GPR3_PCTL_CAN10PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2745 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2746 return Frequency;
2747 }
2748
2749 /* Return FLEXCAN11_CLK frequency */
Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void)2750 static uint32 Clock_Ip_Get_FLEXCAN11_CLK_Frequency(void) {
2751
2752 uint32 Frequency;
2753 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2754 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN11PCTL & GPR3_PCTL_CAN11PCTL_PCTL_MASK) >> GPR3_PCTL_CAN11PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2755 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2756 return Frequency;
2757 }
2758
2759 /* Return FLEXCAN12_CLK frequency */
Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void)2760 static uint32 Clock_Ip_Get_FLEXCAN12_CLK_Frequency(void) {
2761
2762 uint32 Frequency;
2763 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2764 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN12PCTL & GPR3_PCTL_CAN12PCTL_PCTL_MASK) >> GPR3_PCTL_CAN12PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2765 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2766 return Frequency;
2767 }
2768
2769 /* Return FLEXCAN13_CLK frequency */
Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void)2770 static uint32 Clock_Ip_Get_FLEXCAN13_CLK_Frequency(void) {
2771
2772 uint32 Frequency;
2773 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2774 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN13PCTL & GPR3_PCTL_CAN13PCTL_PCTL_MASK) >> GPR3_PCTL_CAN13PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2775 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2776 return Frequency;
2777 }
2778
2779 /* Return FLEXCAN14_CLK frequency */
Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void)2780 static uint32 Clock_Ip_Get_FLEXCAN14_CLK_Frequency(void) {
2781
2782 uint32 Frequency;
2783 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2784 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN14PCTL & GPR3_PCTL_CAN14PCTL_PCTL_MASK) >> GPR3_PCTL_CAN14PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2785 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2786 return Frequency;
2787 }
2788
2789 /* Return FLEXCAN15_CLK frequency */
Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void)2790 static uint32 Clock_Ip_Get_FLEXCAN15_CLK_Frequency(void) {
2791
2792 uint32 Frequency;
2793 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2794 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN15PCTL & GPR3_PCTL_CAN15PCTL_PCTL_MASK) >> GPR3_PCTL_CAN15PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2795 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2796 return Frequency;
2797 }
2798
2799 /* Return FLEXCAN16_CLK frequency */
Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void)2800 static uint32 Clock_Ip_Get_FLEXCAN16_CLK_Frequency(void) {
2801
2802 uint32 Frequency;
2803 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2804 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN16PCTL & GPR3_PCTL_CAN16PCTL_PCTL_MASK) >> GPR3_PCTL_CAN16PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2805 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2806 return Frequency;
2807 }
2808
2809 /* Return FLEXCAN17_CLK frequency */
Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void)2810 static uint32 Clock_Ip_Get_FLEXCAN17_CLK_Frequency(void) {
2811
2812 uint32 Frequency;
2813 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2814 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN17PCTL & GPR3_PCTL_CAN17PCTL_PCTL_MASK) >> GPR3_PCTL_CAN17PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2815 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2816 return Frequency;
2817 }
2818
2819 /* Return FLEXCAN18_CLK frequency */
Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void)2820 static uint32 Clock_Ip_Get_FLEXCAN18_CLK_Frequency(void) {
2821
2822 uint32 Frequency;
2823 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2824 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN18PCTL & GPR3_PCTL_CAN18PCTL_PCTL_MASK) >> GPR3_PCTL_CAN18PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2825 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2826 return Frequency;
2827 }
2828
2829 /* Return FLEXCAN19_CLK frequency */
Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void)2830 static uint32 Clock_Ip_Get_FLEXCAN19_CLK_Frequency(void) {
2831
2832 uint32 Frequency;
2833 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2834 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN19PCTL & GPR3_PCTL_CAN19PCTL_PCTL_MASK) >> GPR3_PCTL_CAN19PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2835 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2836 return Frequency;
2837 }
2838
2839 /* Return FLEXCAN20_CLK frequency */
Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void)2840 static uint32 Clock_Ip_Get_FLEXCAN20_CLK_Frequency(void) {
2841
2842 uint32 Frequency;
2843 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2844 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN20PCTL & GPR3_PCTL_CAN20PCTL_PCTL_MASK) >> GPR3_PCTL_CAN20PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2845 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2846 return Frequency;
2847 }
2848
2849 /* Return FLEXCAN21_CLK frequency */
Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void)2850 static uint32 Clock_Ip_Get_FLEXCAN21_CLK_Frequency(void) {
2851
2852 uint32 Frequency;
2853 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2854 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN21PCTL & GPR3_PCTL_CAN21PCTL_PCTL_MASK) >> GPR3_PCTL_CAN21PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2855 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2856 return Frequency;
2857 }
2858
2859 /* Return FLEXCAN22_CLK frequency */
Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void)2860 static uint32 Clock_Ip_Get_FLEXCAN22_CLK_Frequency(void) {
2861
2862 uint32 Frequency;
2863 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2864 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN22PCTL & GPR3_PCTL_CAN22PCTL_PCTL_MASK) >> GPR3_PCTL_CAN22PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2865 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2866 return Frequency;
2867 }
2868
2869 /* Return FLEXCAN23_CLK frequency */
Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void)2870 static uint32 Clock_Ip_Get_FLEXCAN23_CLK_Frequency(void) {
2871
2872 uint32 Frequency;
2873 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
2874 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->CAN23PCTL & GPR3_PCTL_CAN23PCTL_PCTL_MASK) >> GPR3_PCTL_CAN23PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2875 Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2876 return Frequency;
2877 }
2878
2879 /* Return IIIC0_CLK frequency */
Clock_Ip_Get_IIIC0_CLK_Frequency(void)2880 static uint32 Clock_Ip_Get_IIIC0_CLK_Frequency(void) {
2881
2882 uint32 Frequency;
2883 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2884 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2885 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2886 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->I3C0PCTL & GPR0_PCTL_I3C0PCTL_PCTL_MASK) >> GPR0_PCTL_I3C0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2887 return Frequency;
2888 }
2889
2890 /* Return IIIC1_CLK frequency */
Clock_Ip_Get_IIIC1_CLK_Frequency(void)2891 static uint32 Clock_Ip_Get_IIIC1_CLK_Frequency(void) {
2892
2893 uint32 Frequency;
2894 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2895 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2896 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2897 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->I3C1PCTL & GPR1_PCTL_I3C1PCTL_PCTL_MASK) >> GPR1_PCTL_I3C1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2898 return Frequency;
2899 }
2900
2901 /* Return IIIC2_CLK frequency */
Clock_Ip_Get_IIIC2_CLK_Frequency(void)2902 static uint32 Clock_Ip_Get_IIIC2_CLK_Frequency(void) {
2903
2904 uint32 Frequency;
2905 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
2906 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2907 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2908 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->I3C2PCTL & GPR4_PCTL_I3C2PCTL_PCTL_MASK) >> GPR4_PCTL_I3C2PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2909 return Frequency;
2910 }
2911
2912
2913 /* Return P4_LIN_BAUD_CLK frequency */
Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void)2914 static uint32 Clock_Ip_Get_P4_LIN_BAUD_CLK_Frequency(void) {
2915
2916 uint32 Frequency;
2917 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2918 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2919 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2920 return Frequency;
2921 }
2922
2923 /* Return LIN6_CLK frequency */
Clock_Ip_Get_LIN6_CLK_Frequency(void)2924 static uint32 Clock_Ip_Get_LIN6_CLK_Frequency(void) {
2925
2926 uint32 Frequency;
2927 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2928 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN6PCTL & GPR4_PCTL_LIN6PCTL_PCTL_MASK) >> GPR4_PCTL_LIN6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2929 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2930 return Frequency;
2931 }
2932
2933 /* Return LIN7_CLK frequency */
Clock_Ip_Get_LIN7_CLK_Frequency(void)2934 static uint32 Clock_Ip_Get_LIN7_CLK_Frequency(void) {
2935
2936 uint32 Frequency;
2937 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2938 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN7PCTL & GPR4_PCTL_LIN7PCTL_PCTL_MASK) >> GPR4_PCTL_LIN7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2939 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2940 return Frequency;
2941 }
2942
2943 /* Return LIN8_CLK frequency */
Clock_Ip_Get_LIN8_CLK_Frequency(void)2944 static uint32 Clock_Ip_Get_LIN8_CLK_Frequency(void) {
2945
2946 uint32 Frequency;
2947 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
2948 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->LIN8PCTL & GPR4_PCTL_LIN8PCTL_PCTL_MASK) >> GPR4_PCTL_LIN8PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
2949 Frequency /= (((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2950 return Frequency;
2951 }
2952
2953 /* Return P0_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void)2954 static uint32 Clock_Ip_Get_P0_CLKOUT_SRC_CLK_Frequency(void) {
2955
2956 return Clock_Ip_apfFreqTableCLKOUT0SEL[((IP_GPR0->CLKOUT0SEL & GPR0_CLKOUT0SEL_MUXSEL_MASK) >> GPR0_CLKOUT0SEL_MUXSEL_SHIFT)]();/* Selector value */
2957 }
2958
2959 /* Return P0_CTU_PER_CLK frequency */
Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void)2960 static uint32 Clock_Ip_Get_P0_CTU_PER_CLK_Frequency(void) {
2961
2962 uint32 Frequency;
2963 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2964 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2965 Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2966 return Frequency;
2967 }
2968
2969 /* Return P0_DSPI_MSC_CLK frequency */
Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void)2970 static uint32 Clock_Ip_Get_P0_DSPI_MSC_CLK_Frequency(void) {
2971
2972 uint32 Frequency;
2973 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
2974 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
2975 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
2976 return Frequency;
2977 }
2978
2979 /* Return P0_EMIOS_LCU_CLK frequency */
Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void)2980 static uint32 Clock_Ip_Get_P0_EMIOS_LCU_CLK_Frequency(void) {
2981
2982 uint32 Frequency;
2983 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
2984 return Frequency;
2985 }
2986
2987 /* Return P0_GTM_CLK frequency */
Clock_Ip_Get_P0_GTM_CLK_Frequency(void)2988 static uint32 Clock_Ip_Get_P0_GTM_CLK_Frequency(void) {
2989
2990 uint32 Frequency;
2991 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
2992 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
2993 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
2994 return Frequency;
2995 }
2996
2997 /* Return P0_GTM_NOC_CLK frequency */
Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void)2998 static uint32 Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency(void) {
2999
3000 uint32 Frequency;
3001 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3002 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3003 Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3004 return Frequency;
3005 }
3006
3007 /* Return P0_GTM_TS_CLK frequency */
Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void)3008 static uint32 Clock_Ip_Get_P0_GTM_TS_CLK_Frequency(void) {
3009
3010 uint32 Frequency;
3011 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3012 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3013 Frequency /= ((((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 5U); /* Apply divider value */
3014 return Frequency;
3015 }
3016
3017 /* Return P0_LIN_CLK frequency */
Clock_Ip_Get_P0_LIN_CLK_Frequency(void)3018 static uint32 Clock_Ip_Get_P0_LIN_CLK_Frequency(void) {
3019
3020 uint32 Frequency;
3021 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3022 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3023 Frequency /= ((((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3024 return Frequency;
3025 }
3026
3027
3028 /* Return P0_PSI5_125K_CLK frequency */
Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void)3029 static uint32 Clock_Ip_Get_P0_PSI5_125K_CLK_Frequency(void) {
3030
3031 uint32 Frequency;
3032 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3033 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3034 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3035 return Frequency;
3036 }
3037
3038 /* Return P0_PSI5_189K_CLK frequency */
Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void)3039 static uint32 Clock_Ip_Get_P0_PSI5_189K_CLK_Frequency(void) {
3040
3041 uint32 Frequency;
3042 uint32 Multi;
3043 uint32 Div;
3044 uint32 Fin;
3045
3046 if(((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 1U)
3047 {
3048 Multi = 10U;
3049 }
3050 else if(((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 2U)
3051 {
3052 Multi = 100U;
3053 }
3054 else if(((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 3U)
3055 {
3056 Multi = 1000U;
3057 }
3058 else
3059 {
3060 Multi = 1U;
3061 }
3062 Fin = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3063 Fin &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> MC_CGM_MUX_2_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3064 Div = (((IP_MC_CGM_0->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3065
3066 if(0U == Fin)
3067 {
3068 Frequency = 0;
3069 }
3070 else
3071 {
3072 if (Multi == ((uint32)(Multi * Fin) / Fin))
3073 {
3074 Frequency = ((Multi * Fin)/Div); /* calculate when Multi * Fin <= 2^32-1 */
3075 }
3076 else if (Div == ((uint32)(Fin/Div) * Fin))
3077 {
3078 Frequency = ((Fin/Div)*Multi); /* calculate when Fin % Div == 0*/
3079 }
3080 else
3081 {
3082 Frequency = (Fin/Div)*Multi; /*calculate with even part*/
3083 Frequency += ((Fin - ((Fin/Div)*Div) )*Multi)/Div; /*calculate with remainder*/
3084 }
3085 }
3086 return Frequency;
3087 }
3088
3089 /* Return P0_PSI5_S_BAUD_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void)3090 static uint32 Clock_Ip_Get_P0_PSI5_S_BAUD_CLK_Frequency(void) {
3091
3092 uint32 Frequency;
3093 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3094 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3095 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3096 return Frequency;
3097 }
3098
3099 /* Return P0_PSI5_S_CORE_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void)3100 static uint32 Clock_Ip_Get_P0_PSI5_S_CORE_CLK_Frequency(void) {
3101
3102 uint32 Frequency;
3103 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3104 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3105 Frequency /= ((((IP_MC_CGM_0->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3106 return Frequency;
3107 }
3108
3109 /* Return P0_PSI5_S_TRIG1_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void)3110 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG1_CLK_Frequency(void) {
3111
3112 uint32 Frequency;
3113 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3114 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3115 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> MC_CGM_MUX_3_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3116 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DIV_MASK) >> MC_CGM_MUX_3_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3117 return Frequency;
3118 }
3119
3120 /* Return P0_PSI5_S_TRIG2_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void)3121 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG2_CLK_Frequency(void) {
3122
3123 uint32 Frequency;
3124 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3125 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3126 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DE_MASK) >> MC_CGM_MUX_3_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3127 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DIV_MASK) >> MC_CGM_MUX_3_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3128 return Frequency;
3129 }
3130
3131 /* Return P0_PSI5_S_TRIG3_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void)3132 static uint32 Clock_Ip_Get_P0_PSI5_S_TRIG3_CLK_Frequency(void) {
3133
3134 uint32 Frequency;
3135 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3136 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3137 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> MC_CGM_MUX_3_DC_3_DE_SHIFT)]; /* Divider enable/disable */
3138 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3139 return Frequency;
3140 }
3141
3142 /* Return P0_PSI5_S_UART_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void)3143 static uint32 Clock_Ip_Get_P0_PSI5_S_UART_CLK_Frequency(void) {
3144
3145 uint32 Frequency;
3146 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3147 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> MC_CGM_MUX_2_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3148 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3149 return Frequency;
3150 }
3151
3152 /* Return P0_PSI5_S_WDOG0_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void)3153 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG0_CLK_Frequency(void) {
3154
3155 uint32 Frequency;
3156 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3157 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3158 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DE_MASK) >> MC_CGM_MUX_3_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3159 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DIV_MASK) >> MC_CGM_MUX_3_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3160 return Frequency;
3161 }
3162
3163 /* Return P0_PSI5_S_WDOG1_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void)3164 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG1_CLK_Frequency(void) {
3165
3166 uint32 Frequency;
3167 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3168 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3169 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DE_MASK) >> MC_CGM_MUX_3_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3170 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DIV_MASK) >> MC_CGM_MUX_3_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3171 return Frequency;
3172 }
3173
3174 /* Return P0_PSI5_S_WDOG2_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void)3175 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG2_CLK_Frequency(void) {
3176
3177 uint32 Frequency;
3178 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3179 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3180 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DE_MASK) >> MC_CGM_MUX_3_DC_6_DE_SHIFT)]; /* Divider enable/disable */
3181 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DIV_MASK) >> MC_CGM_MUX_3_DC_6_DIV_SHIFT) + 1U); /* Apply divider value */
3182 return Frequency;
3183 }
3184
3185 /* Return P0_PSI5_S_WDOG3_CLK frequency */
Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void)3186 static uint32 Clock_Ip_Get_P0_PSI5_S_WDOG3_CLK_Frequency(void) {
3187
3188 uint32 Frequency;
3189 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX0;
3190 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3191 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DE_MASK) >> MC_CGM_MUX_3_DC_7_DE_SHIFT)]; /* Divider enable/disable */
3192 Frequency /= (((IP_MC_CGM_0->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DIV_MASK) >> MC_CGM_MUX_3_DC_7_DIV_SHIFT) + 1U); /* Apply divider value */
3193 return Frequency;
3194 }
3195
3196 /* Return P0_REG_INTF_2X_CLK frequency */
Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void)3197 static uint32 Clock_Ip_Get_P0_REG_INTF_2X_CLK_Frequency(void) {
3198
3199 uint32 Frequency;
3200 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3201 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> MC_CGM_MUX_1_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3202 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3203 return Frequency;
3204 }
3205
3206 /* Return P1_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void)3207 static uint32 Clock_Ip_Get_P1_CLKOUT_SRC_CLK_Frequency(void) {
3208
3209 return Clock_Ip_apfFreqTableCLKOUT1SEL[((IP_GPR1->CLKOUT1SEL & GPR1_CLKOUT1SEL_MUXSEL_MASK) >> GPR1_CLKOUT1SEL_MUXSEL_SHIFT)]();/* Selector value */
3210 }
3211
3212
3213 /* Return P1_DSPI60_CLK frequency */
Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void)3214 static uint32 Clock_Ip_Get_P1_DSPI60_CLK_Frequency(void) {
3215
3216 uint32 Frequency;
3217 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3218 return Frequency;
3219 }
3220
3221 /* Return ETH_TS_CLK frequency */
Clock_Ip_Get_ETH_TS_CLK_Frequency(void)3222 static uint32 Clock_Ip_Get_ETH_TS_CLK_Frequency(void) {
3223
3224 uint32 Frequency;
3225 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3226 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3227 Frequency /= (((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3228 return Frequency;
3229 }
3230
3231 /* Return ETH_TS_DIV4_CLK frequency */
Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void)3232 static uint32 Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency(void) {
3233
3234 uint32 Frequency;
3235 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3236 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3237 Frequency /= ((((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U) * 4U); /* Apply divider value */
3238 return Frequency;
3239 }
3240
3241 /* Return ETH0_REF_RMII_CLK frequency */
Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void)3242 static uint32 Clock_Ip_Get_ETH0_REF_RMII_CLK_Frequency(void) {
3243
3244 uint32 Frequency;
3245 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3246 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DE_MASK) >> MC_CGM_MUX_7_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3247 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_2 & MC_CGM_MUX_7_DC_2_DIV_MASK) >> MC_CGM_MUX_7_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3248 return Frequency;
3249 }
3250
3251 /* Return ETH0_RX_MII_CLK frequency */
Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void)3252 static uint32 Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency(void) {
3253
3254 uint32 Frequency;
3255 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3256 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3257 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3258 return Frequency;
3259 }
3260
3261 /* Return ETH0_RX_RGMII_CLK frequency */
Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void)3262 static uint32 Clock_Ip_Get_ETH0_RX_RGMII_CLK_Frequency(void) {
3263
3264 uint32 Frequency;
3265 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3266 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DE_MASK) >> MC_CGM_MUX_7_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3267 Frequency /= (((IP_MC_CGM_1->MUX_7_DC_1 & MC_CGM_MUX_7_DC_1_DIV_MASK) >> MC_CGM_MUX_7_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3268 return Frequency;
3269 }
3270
3271 /* Return ETH0_TX_RGMII_CLK frequency */
Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void)3272 static uint32 Clock_Ip_Get_ETH0_TX_RGMII_CLK_Frequency(void) {
3273
3274 uint32 Frequency;
3275 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
3276 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> MC_CGM_MUX_6_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3277 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DIV_MASK) >> MC_CGM_MUX_6_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3278 return Frequency;
3279 }
3280
3281 /* Return ETH0_PS_TX_CLK frequency */
Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency(void)3282 static uint32 Clock_Ip_Get_ETH0_PS_TX_CLK_Frequency(void) {
3283
3284 uint32 Frequency;
3285 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_6_CSS & MC_CGM_MUX_6_CSS_SELSTAT_MASK) >> MC_CGM_MUX_6_CSS_SELSTAT_SHIFT)]();/* Selector value */
3286 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DE_MASK) >> MC_CGM_MUX_6_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3287 Frequency /= (((IP_MC_CGM_1->MUX_6_DC_1 & MC_CGM_MUX_6_DC_1_DIV_MASK) >> MC_CGM_MUX_6_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3288 return Frequency;
3289 }
3290
3291 /* Return ETH1_REF_RMII_CLK frequency */
Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void)3292 static uint32 Clock_Ip_Get_ETH1_REF_RMII_CLK_Frequency(void) {
3293
3294 uint32 Frequency;
3295 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3296 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_2 & MC_CGM_MUX_9_DC_2_DE_MASK) >> MC_CGM_MUX_9_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3297 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_2 & MC_CGM_MUX_9_DC_2_DIV_MASK) >> MC_CGM_MUX_9_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3298 return Frequency;
3299 }
3300
3301 /* Return ETH1_RX_MII_CLK frequency */
Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void)3302 static uint32 Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency(void) {
3303
3304 uint32 Frequency;
3305 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3306 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC_CGM_MUX_9_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3307 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3308 return Frequency;
3309 }
3310
3311 /* Return ETH1_RX_RGMII_CLK frequency */
Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void)3312 static uint32 Clock_Ip_Get_ETH1_RX_RGMII_CLK_Frequency(void) {
3313
3314 uint32 Frequency;
3315 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3316 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3317 Frequency /= (((IP_MC_CGM_1->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3318 return Frequency;
3319 }
3320
3321 /* Return ETH1_TX_MII_CLK frequency */
Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void)3322 static uint32 Clock_Ip_Get_ETH1_TX_MII_CLK_Frequency(void) {
3323
3324 uint32 Frequency;
3325 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3326 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3327 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3328 return Frequency;
3329 }
3330
3331 /* Return ETH1_TX_RGMII_CLK frequency */
Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void)3332 static uint32 Clock_Ip_Get_ETH1_TX_RGMII_CLK_Frequency(void) {
3333
3334 uint32 Frequency;
3335 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3336 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> MC_CGM_MUX_8_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3337 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3338 return Frequency;
3339 }
3340
3341 /* Return ETH1_PS_TX_CLK frequency */
Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency(void)3342 static uint32 Clock_Ip_Get_ETH1_PS_TX_CLK_Frequency(void) {
3343
3344 uint32 Frequency;
3345 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3346 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DE_MASK) >> MC_CGM_MUX_8_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3347 Frequency /= (((IP_MC_CGM_1->MUX_8_DC_1 & MC_CGM_MUX_8_DC_1_DIV_MASK) >> MC_CGM_MUX_8_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3348 return Frequency;
3349 }
3350
3351 /* Return P1_LFAST1_REF_CLK frequency */
Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void)3352 static uint32 Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(void) {
3353
3354 uint32 Frequency;
3355 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_12_CSS & MC_CGM_MUX_12_CSS_SELSTAT_MASK) >> MC_CGM_MUX_12_CSS_SELSTAT_SHIFT)]();/* Selector value */
3356 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> MC_CGM_MUX_12_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3357 Frequency /= (((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3358 return Frequency;
3359 }
3360
3361 /* Return P1_NETC_AXI_CLK frequency */
Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void)3362 static uint32 Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency(void) {
3363
3364 uint32 Frequency;
3365 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_14_CSS & MC_CGM_MUX_14_CSS_SELSTAT_MASK) >> MC_CGM_MUX_14_CSS_SELSTAT_SHIFT)]();/* Selector value */
3366 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DE_MASK) >> MC_CGM_MUX_14_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3367 Frequency /= (((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DIV_MASK) >> MC_CGM_MUX_14_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3368 return Frequency;
3369 }
3370
3371 /* Return P1_LIN_CLK frequency */
Clock_Ip_Get_P1_LIN_CLK_Frequency(void)3372 static uint32 Clock_Ip_Get_P1_LIN_CLK_Frequency(void) {
3373
3374 uint32 Frequency;
3375 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3376 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC_CGM_MUX_4_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3377 Frequency /= ((((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3378 return Frequency;
3379 }
3380
3381 /* Return P3_AES_CLK frequency */
Clock_Ip_Get_P3_AES_CLK_Frequency(void)3382 static uint32 Clock_Ip_Get_P3_AES_CLK_Frequency(void) {
3383
3384 uint32 Frequency;
3385 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3386 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3387 Frequency /= (((IP_MC_CGM_3->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3388 return Frequency;
3389 }
3390
3391 /* Return P3_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void)3392 static uint32 Clock_Ip_Get_P3_CLKOUT_SRC_CLK_Frequency(void) {
3393
3394 return Clock_Ip_apfFreqTableCLKOUT4SEL[((IP_GPR3->CLKOUT4SEL & GPR3_CLKOUT4SEL_MUXSEL_MASK) >> GPR3_CLKOUT4SEL_MUXSEL_SHIFT)]();/* Selector value */
3395 }
3396
3397
3398 /* Return P3_DBG_TS_CLK frequency */
Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void)3399 static uint32 Clock_Ip_Get_P3_DBG_TS_CLK_Frequency(void) {
3400
3401 uint32 Frequency;
3402 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3403 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3404 Frequency /= (((IP_MC_CGM_3->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3405 return Frequency;
3406 }
3407
3408 /* Return P3_REG_INTF_CLK frequency */
Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void)3409 static uint32 Clock_Ip_Get_P3_REG_INTF_CLK_Frequency(void) {
3410
3411 uint32 Frequency;
3412 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3413 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3414 Frequency /= (((IP_MC_CGM_3->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3415 return Frequency;
3416 }
3417
3418 /* Return P4_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void)3419 static uint32 Clock_Ip_Get_P4_CLKOUT_SRC_CLK_Frequency(void) {
3420
3421 return Clock_Ip_apfFreqTableCLKOUT2SEL[((IP_GPR4->CLKOUT2SEL & GPR4_CLKOUT2SEL_MUXSEL_MASK) >> GPR4_CLKOUT2SEL_MUXSEL_SHIFT)]();/* Selector value */
3422 }
3423
3424
3425 /* Return P4_DSPI60_CLK frequency */
Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void)3426 static uint32 Clock_Ip_Get_P4_DSPI60_CLK_Frequency(void) {
3427
3428 uint32 Frequency;
3429 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3430 return Frequency;
3431 }
3432
3433 /* Return P4_EMIOS_LCU_CLK frequency */
Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void)3434 static uint32 Clock_Ip_Get_P4_EMIOS_LCU_CLK_Frequency(void) {
3435
3436 uint32 Frequency;
3437 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_11_CSS & MC_CGM_MUX_11_CSS_SELSTAT_MASK) >> MC_CGM_MUX_11_CSS_SELSTAT_SHIFT)]();/* Selector value */
3438 return Frequency;
3439 }
3440
3441 /* Return P4_LIN_CLK frequency */
Clock_Ip_Get_P4_LIN_CLK_Frequency(void)3442 static uint32 Clock_Ip_Get_P4_LIN_CLK_Frequency(void) {
3443
3444 uint32 Frequency;
3445 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_8_CSS & MC_CGM_MUX_8_CSS_SELSTAT_MASK) >> MC_CGM_MUX_8_CSS_SELSTAT_SHIFT)]();/* Selector value */
3446 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DE_MASK) >> MC_CGM_MUX_8_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3447 Frequency /= ((((IP_MC_CGM_4->MUX_8_DC_0 & MC_CGM_MUX_8_DC_0_DIV_MASK) >> MC_CGM_MUX_8_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3448 return Frequency;
3449 }
3450
3451 /* Return P4_PSI5_125K_CLK frequency */
Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void)3452 static uint32 Clock_Ip_Get_P4_PSI5_125K_CLK_Frequency(void) {
3453
3454 uint32 Frequency;
3455 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3456 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DE_MASK) >> MC_CGM_MUX_2_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3457 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_1 & MC_CGM_MUX_2_DC_1_DIV_MASK) >> MC_CGM_MUX_2_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3458 return Frequency;
3459 }
3460
3461 /* Return P4_PSI5_189K_CLK frequency */
Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void)3462 static uint32 Clock_Ip_Get_P4_PSI5_189K_CLK_Frequency(void) {
3463
3464 uint32 Frequency;
3465 uint32 Multi;
3466 uint32 Div;
3467 uint32 Fin;
3468
3469 if(((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 1U)
3470 {
3471 Multi = 10U;
3472 }
3473 else if(((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 2U)
3474 {
3475 Multi = 100U;
3476 }
3477 else if(((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_FMT_MASK) >> MC_CGM_MUX_2_DC_2_DIV_FMT_SHIFT) == 3U)
3478 {
3479 Multi = 1000U;
3480 }
3481 else
3482 {
3483 Multi = 1U;
3484 }
3485 Fin = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3486 Fin &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DE_MASK) >> MC_CGM_MUX_2_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3487 Div = (((IP_MC_CGM_4->MUX_2_DC_2 & MC_CGM_MUX_2_DC_2_DIV_MASK) >> MC_CGM_MUX_2_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3488
3489 if(0U == Fin)
3490 {
3491 Frequency = 0;
3492 }
3493 else
3494 {
3495 if (Multi == ((uint32)(Multi * Fin) / Fin))
3496 {
3497 Frequency = ((Multi * Fin)/Div); /* calculate when Multi * Fin <= 2^32-1 */
3498 }
3499 else if (Div == ((uint32)(Fin/Div) * Fin))
3500 {
3501 Frequency = ((Fin/Div)*Multi); /* calculate when Fin % Div == 0*/
3502 }
3503 else
3504 {
3505 Frequency = (Fin/Div)*Multi; /*calculate with even part*/
3506 Frequency += ((Fin - ((Fin/Div)*Div) )*Multi)/Div; /*calculate with remainder*/
3507 }
3508 }
3509 return Frequency;
3510 }
3511
3512 /* Return P4_PSI5_S_BAUD_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void)3513 static uint32 Clock_Ip_Get_P4_PSI5_S_BAUD_CLK_Frequency(void) {
3514
3515 uint32 Frequency;
3516 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3517 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3518 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3519 return Frequency;
3520 }
3521
3522 /* Return P4_PSI5_S_CORE_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void)3523 static uint32 Clock_Ip_Get_P4_PSI5_S_CORE_CLK_Frequency(void) {
3524
3525 uint32 Frequency;
3526 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3527 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DE_MASK) >> MC_CGM_MUX_2_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3528 Frequency /= ((((IP_MC_CGM_4->MUX_2_DC_5 & MC_CGM_MUX_2_DC_5_DIV_MASK) >> MC_CGM_MUX_2_DC_5_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3529 return Frequency;
3530 }
3531
3532 /* Return P4_PSI5_S_TRIG0_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void)3533 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG0_CLK_Frequency(void) {
3534
3535 uint32 Frequency;
3536 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3537 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3538 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC_CGM_MUX_3_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3539 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3540 return Frequency;
3541 }
3542
3543 /* Return P4_PSI5_S_TRIG1_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void)3544 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG1_CLK_Frequency(void) {
3545
3546 uint32 Frequency;
3547 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3548 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3549 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DE_MASK) >> MC_CGM_MUX_3_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3550 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_1 & MC_CGM_MUX_3_DC_1_DIV_MASK) >> MC_CGM_MUX_3_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3551 return Frequency;
3552 }
3553
3554 /* Return P4_PSI5_S_TRIG2_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void)3555 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG2_CLK_Frequency(void) {
3556
3557 uint32 Frequency;
3558 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3559 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3560 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DE_MASK) >> MC_CGM_MUX_3_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3561 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_2 & MC_CGM_MUX_3_DC_2_DIV_MASK) >> MC_CGM_MUX_3_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3562 return Frequency;
3563 }
3564
3565 /* Return P4_PSI5_S_TRIG3_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void)3566 static uint32 Clock_Ip_Get_P4_PSI5_S_TRIG3_CLK_Frequency(void) {
3567
3568 uint32 Frequency;
3569 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3570 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3571 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DE_MASK) >> MC_CGM_MUX_3_DC_3_DE_SHIFT)]; /* Divider enable/disable */
3572 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_3 & MC_CGM_MUX_3_DC_3_DIV_MASK) >> MC_CGM_MUX_3_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3573 return Frequency;
3574 }
3575
3576 /* Return P4_PSI5_S_UART_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void)3577 static uint32 Clock_Ip_Get_P4_PSI5_S_UART_CLK_Frequency(void) {
3578
3579 uint32 Frequency;
3580 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3581 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DE_MASK) >> MC_CGM_MUX_2_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3582 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_4 & MC_CGM_MUX_2_DC_4_DIV_MASK) >> MC_CGM_MUX_2_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3583 return Frequency;
3584 }
3585
3586 /* Return P4_PSI5_S_WDOG0_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void)3587 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG0_CLK_Frequency(void) {
3588
3589 uint32 Frequency;
3590 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3591 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3592 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DE_MASK) >> MC_CGM_MUX_3_DC_4_DE_SHIFT)]; /* Divider enable/disable */
3593 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_4 & MC_CGM_MUX_3_DC_4_DIV_MASK) >> MC_CGM_MUX_3_DC_4_DIV_SHIFT) + 1U); /* Apply divider value */
3594 return Frequency;
3595 }
3596
3597 /* Return P4_PSI5_S_WDOG1_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void)3598 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG1_CLK_Frequency(void) {
3599
3600 uint32 Frequency;
3601 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3602 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3603 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DE_MASK) >> MC_CGM_MUX_3_DC_5_DE_SHIFT)]; /* Divider enable/disable */
3604 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_5 & MC_CGM_MUX_3_DC_5_DIV_MASK) >> MC_CGM_MUX_3_DC_5_DIV_SHIFT) + 1U); /* Apply divider value */
3605 return Frequency;
3606 }
3607
3608 /* Return P4_PSI5_S_WDOG2_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void)3609 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG2_CLK_Frequency(void) {
3610
3611 uint32 Frequency;
3612 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3613 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3614 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DE_MASK) >> MC_CGM_MUX_3_DC_6_DE_SHIFT)]; /* Divider enable/disable */
3615 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_6 & MC_CGM_MUX_3_DC_6_DIV_MASK) >> MC_CGM_MUX_3_DC_6_DIV_SHIFT) + 1U); /* Apply divider value */
3616 return Frequency;
3617 }
3618
3619 /* Return P4_PSI5_S_WDOG3_CLK frequency */
Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void)3620 static uint32 Clock_Ip_Get_P4_PSI5_S_WDOG3_CLK_Frequency(void) {
3621
3622 uint32 Frequency;
3623 Clock_Ip_u32PSI5_S_UTILIndex = CLOCK_IP_CLKPSI5_S_UTIL_INDEX1;
3624 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_3_CSS & MC_CGM_MUX_3_CSS_SELSTAT_MASK) >> MC_CGM_MUX_3_CSS_SELSTAT_SHIFT)]();/* Selector value */
3625 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DE_MASK) >> MC_CGM_MUX_3_DC_7_DE_SHIFT)]; /* Divider enable/disable */
3626 Frequency /= (((IP_MC_CGM_4->MUX_3_DC_7 & MC_CGM_MUX_3_DC_7_DIV_MASK) >> MC_CGM_MUX_3_DC_7_DIV_SHIFT) + 1U); /* Apply divider value */
3627 return Frequency;
3628 }
3629
3630 /* Return P4_QSPI0_2X_CLK frequency */
Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void)3631 static uint32 Clock_Ip_Get_P4_QSPI0_2X_CLK_Frequency(void) {
3632
3633 uint32 Frequency;
3634 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3635 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3636 Frequency /= (((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3637 return Frequency;
3638 }
3639
3640 /* Return P4_QSPI0_1X_CLK frequency */
Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void)3641 static uint32 Clock_Ip_Get_P4_QSPI0_1X_CLK_Frequency(void) {
3642
3643 uint32 Frequency;
3644 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3645 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC_CGM_MUX_7_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3646 Frequency /= ((((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3647 return Frequency;
3648 }
3649
3650 /* Return P4_QSPI1_2X_CLK frequency */
Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void)3651 static uint32 Clock_Ip_Get_P4_QSPI1_2X_CLK_Frequency(void) {
3652
3653 uint32 Frequency;
3654 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3655 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3656 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3657 return Frequency;
3658 }
3659
3660 /* Return P4_QSPI1_1X_CLK frequency */
Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void)3661 static uint32 Clock_Ip_Get_P4_QSPI1_1X_CLK_Frequency(void) {
3662
3663 uint32 Frequency;
3664 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3665 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DE_MASK) >> MC_CGM_MUX_9_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3666 Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3667 return Frequency;
3668 }
3669
3670 /* Return P4_REG_INTF_2X_CLK frequency */
Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void)3671 static uint32 Clock_Ip_Get_P4_REG_INTF_2X_CLK_Frequency(void) {
3672
3673 uint32 Frequency;
3674 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3675 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DE_MASK) >> MC_CGM_MUX_1_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3676 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_1 & MC_CGM_MUX_1_DC_1_DIV_MASK) >> MC_CGM_MUX_1_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3677 return Frequency;
3678 }
3679
3680 /* Return P4_REG_INTF_CLK frequency */
Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void)3681 static uint32 Clock_Ip_Get_P4_REG_INTF_CLK_Frequency(void) {
3682
3683 uint32 Frequency;
3684 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3685 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3686 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3687 return Frequency;
3688 }
3689
3690 /* Return P4_SDHC_IP_CLK frequency */
Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void)3691 static uint32 Clock_Ip_Get_P4_SDHC_IP_CLK_Frequency(void) {
3692
3693 uint32 Frequency;
3694 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)]();/* Selector value */
3695 return Frequency;
3696 }
3697
3698 /* Return P4_SDHC_IP_DIV2_CLK frequency */
Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void)3699 static uint32 Clock_Ip_Get_P4_SDHC_IP_DIV2_CLK_Frequency(void) {
3700
3701 uint32 Frequency;
3702 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_10_CSS & MC_CGM_MUX_10_CSS_SELSTAT_MASK) >> MC_CGM_MUX_10_CSS_SELSTAT_SHIFT)]();/* Selector value */
3703 Frequency = Frequency >> 1U;
3704 return Frequency;
3705 }
3706 /* Return P5_DIPORT_CLK frequency */
Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void)3707 static uint32 Clock_Ip_Get_P5_DIPORT_CLK_Frequency(void) {
3708
3709 uint32 Frequency;
3710 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3711 return Frequency;
3712 }
3713
3714 /* Return P5_AE_CLK frequency */
Clock_Ip_Get_P5_AE_CLK_Frequency(void)3715 static uint32 Clock_Ip_Get_P5_AE_CLK_Frequency(void) {
3716
3717 uint32 Frequency;
3718 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3719 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC_CGM_MUX_5_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3720 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3721 return Frequency;
3722 }
3723
3724 /* Return P5_CANXL_PE_CLK frequency */
Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void)3725 static uint32 Clock_Ip_Get_P5_CANXL_PE_CLK_Frequency(void) {
3726
3727 uint32 Frequency;
3728 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3729 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_1 & MC_CGM_MUX_5_DC_1_DE_MASK) >> MC_CGM_MUX_5_DC_1_DE_SHIFT)]; /* Divider enable/disable */
3730 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_1 & MC_CGM_MUX_5_DC_1_DIV_MASK) >> MC_CGM_MUX_5_DC_1_DIV_SHIFT) + 1U); /* Apply divider value */
3731 return Frequency;
3732 }
3733 /* Return P5_CANXL_CHI_CLK frequency */
Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void)3734 static uint32 Clock_Ip_Get_P5_CANXL_CHI_CLK_Frequency(void) {
3735
3736 uint32 Frequency;
3737 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
3738 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_2 & MC_CGM_MUX_5_DC_2_DE_MASK) >> MC_CGM_MUX_5_DC_2_DE_SHIFT)]; /* Divider enable/disable */
3739 Frequency /= (((IP_MC_CGM_5->MUX_5_DC_2 & MC_CGM_MUX_5_DC_2_DIV_MASK) >> MC_CGM_MUX_5_DC_2_DIV_SHIFT) + 1U); /* Apply divider value */
3740 return Frequency;
3741 }
3742
3743 /* Return P5_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void)3744 static uint32 Clock_Ip_Get_P5_CLKOUT_SRC_CLK_Frequency(void) {
3745
3746 return Clock_Ip_apfFreqTableCLKOUT3SEL[((IP_GPR5->CLKOUT3SEL & GPR5_CLKOUT3SEL_MUXSEL_MASK) >> GPR5_CLKOUT3SEL_MUXSEL_SHIFT)]();/* Selector value */
3747 }
3748
3749
3750 /* Return P5_LIN_CLK frequency */
Clock_Ip_Get_P5_LIN_CLK_Frequency(void)3751 static uint32 Clock_Ip_Get_P5_LIN_CLK_Frequency(void) {
3752
3753 uint32 Frequency;
3754 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3755 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3756 Frequency /= ((((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3757 return Frequency;
3758 }
3759
3760 /* Return P6_REG_INTF_CLK frequency */
Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void)3761 static uint32 Clock_Ip_Get_P6_REG_INTF_CLK_Frequency(void) {
3762
3763 uint32 Frequency;
3764 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_6->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3765 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3766 Frequency /= (((IP_MC_CGM_6->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3767 return Frequency;
3768 }
3769
3770 /* Return PIT0_CLK frequency */
Clock_Ip_Get_PIT0_CLK_Frequency(void)3771 static uint32 Clock_Ip_Get_PIT0_CLK_Frequency(void) {
3772
3773 uint32 Frequency;
3774 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3775 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3776 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3777 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK) >> GPR0_PCTL_EDMA0PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3778 return Frequency;
3779 }
3780
3781 /* Return PIT1_CLK frequency */
Clock_Ip_Get_PIT1_CLK_Frequency(void)3782 static uint32 Clock_Ip_Get_PIT1_CLK_Frequency(void) {
3783
3784 uint32 Frequency;
3785 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3786 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3787 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3788 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_3_MASK) >> GPR1_PCTL_EDMA1PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3789 return Frequency;
3790 }
3791
3792 /* Return PIT4_CLK frequency */
Clock_Ip_Get_PIT4_CLK_Frequency(void)3793 static uint32 Clock_Ip_Get_PIT4_CLK_Frequency(void) {
3794
3795 uint32 Frequency;
3796 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3797 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3798 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3799 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_3_MASK) >> GPR4_PCTL_EDMA4PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3800 return Frequency;
3801 }
3802
3803 /* Return PIT5_CLK frequency */
Clock_Ip_Get_PIT5_CLK_Frequency(void)3804 static uint32 Clock_Ip_Get_PIT5_CLK_Frequency(void) {
3805
3806 uint32 Frequency;
3807 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_5->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3808 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3809 Frequency /= (((IP_MC_CGM_5->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3810 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->EDMA5PCTL & GPR5_PCTL_EDMA5PCTL_PCTL_3_MASK) >> GPR5_PCTL_EDMA5PCTL_PCTL_3_SHIFT)]; /* Apply peripheral clock gate */
3811 return Frequency;
3812 }
3813
3814 /* Return P4_PSI5_1US_CLK frequency */
Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void)3815 static uint32 Clock_Ip_Get_P4_PSI5_1US_CLK_Frequency(void) {
3816
3817 uint32 Frequency;
3818 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3819 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC_CGM_MUX_2_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3820 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3821 return Frequency;
3822 }
3823
3824 /* Return PSI5_1_CLK frequency */
Clock_Ip_Get_PSI5_1_CLK_Frequency(void)3825 static uint32 Clock_Ip_Get_PSI5_1_CLK_Frequency(void) {
3826
3827 uint32 Frequency;
3828 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3829 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->PSI51PCTL & GPR4_PCTL_PSI51PCTL_PCTL_MASK) >> GPR4_PCTL_PSI51PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3830 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3831 return Frequency;
3832 }
3833
3834 /* Return PSI5S_0_CLK frequency */
Clock_Ip_Get_PSI5S_0_CLK_Frequency(void)3835 static uint32 Clock_Ip_Get_PSI5S_0_CLK_Frequency(void) {
3836
3837 uint32 Frequency;
3838 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3839 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->PSI5S0PCTL & GPR0_PCTL_PSI5S0PCTL_PCTL_MASK) >> GPR0_PCTL_PSI5S0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3840 Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3841 return Frequency;
3842 }
3843
3844 /* Return PSI5S_1_CLK frequency */
Clock_Ip_Get_PSI5S_1_CLK_Frequency(void)3845 static uint32 Clock_Ip_Get_PSI5S_1_CLK_Frequency(void) {
3846
3847 uint32 Frequency;
3848 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SHIFT)]();/* Selector value */
3849 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->PSI5S1PCTL & GPR4_PCTL_PSI5S1PCTL_PCTL_MASK) >> GPR4_PCTL_PSI5S1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3850 Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHIFT) + 1U); /* Apply divider value */
3851 return Frequency;
3852 }
3853
3854 /* Return QSPI0_CLK frequency */
Clock_Ip_Get_QSPI0_CLK_Frequency(void)3855 static uint32 Clock_Ip_Get_QSPI0_CLK_Frequency(void) {
3856
3857 uint32 Frequency;
3858 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_7_CSS & MC_CGM_MUX_7_CSS_SELSTAT_MASK) >> MC_CGM_MUX_7_CSS_SELSTAT_SHIFT)]();/* Selector value */
3859 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->QSPI0PCTL & GPR4_PCTL_QSPI0PCTL_PCTL_MASK) >> GPR4_PCTL_QSPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3860 Frequency /= ((((IP_MC_CGM_4->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3861 return Frequency;
3862 }
3863
3864 /* Return QSPI1_CLK frequency */
Clock_Ip_Get_QSPI1_CLK_Frequency(void)3865 static uint32 Clock_Ip_Get_QSPI1_CLK_Frequency(void) {
3866
3867 uint32 Frequency;
3868 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3869 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->QSPI1PCTL & GPR4_PCTL_QSPI1PCTL_PCTL_MASK) >> GPR4_PCTL_QSPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3870 Frequency /= ((((IP_MC_CGM_4->MUX_9_DC_1 & MC_CGM_MUX_9_DC_1_DIV_MASK) >> MC_CGM_MUX_9_DC_1_DIV_SHIFT) + 1U) * 2U); /* Apply divider value */
3871 return Frequency;
3872 }
3873
3874 /* Return RTU0_REG_INTF_CLK frequency */
Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void)3875 static uint32 Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency(void) {
3876
3877 uint32 Frequency;
3878 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_1_CSS & RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3879 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3880 Frequency /= (((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3881 return Frequency;
3882 }
3883
3884 /* Return RTU1_REG_INTF_CLK frequency */
Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void)3885 static uint32 Clock_Ip_Get_RTU1_REG_INTF_CLK_Frequency(void) {
3886
3887 uint32 Frequency;
3888 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU1__MC_CGM->MUX_1_CSS & RTU_MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> RTU_MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3889 Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU1__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DE_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3890 Frequency /= (((IP_RTU1__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3891 return Frequency;
3892 }
3893
3894 /* Return RXLUT_CLK frequency */
Clock_Ip_Get_RXLUT_CLK_Frequency(void)3895 static uint32 Clock_Ip_Get_RXLUT_CLK_Frequency(void) {
3896
3897 uint32 Frequency;
3898 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3899 Frequency = Frequency >> 1U;
3900 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR3_PCTL->RXLUTPCTL & GPR3_PCTL_RXLUTPCTL_PCTL_MASK) >> GPR3_PCTL_RXLUTPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3901 return Frequency;
3902 }
3903 /* Return P4_SDHC_CLK frequency */
Clock_Ip_Get_P4_SDHC_CLK_Frequency(void)3904 static uint32 Clock_Ip_Get_P4_SDHC_CLK_Frequency(void) {
3905
3906 uint32 Frequency;
3907 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3908 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3909 return Frequency;
3910 }
3911
3912 /* Return SDHC0_CLK frequency */
Clock_Ip_Get_SDHC0_CLK_Frequency(void)3913 static uint32 Clock_Ip_Get_SDHC0_CLK_Frequency(void) {
3914
3915 uint32 Frequency;
3916 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_9_CSS & MC_CGM_MUX_9_CSS_SELSTAT_MASK) >> MC_CGM_MUX_9_CSS_SELSTAT_SHIFT)]();/* Selector value */
3917 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SDHCPCTL & GPR4_PCTL_SDHCPCTL_PCTL_MASK) >> GPR4_PCTL_SDHCPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3918 Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3919 return Frequency;
3920 }
3921
3922 /* Return SINC_CLK frequency */
Clock_Ip_Get_SINC_CLK_Frequency(void)3923 static uint32 Clock_Ip_Get_SINC_CLK_Frequency(void) {
3924
3925 uint32 Frequency;
3926 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_0->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
3927 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
3928 Frequency /= (((IP_MC_CGM_0->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
3929 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->SINCPCTL & GPR0_PCTL_SINCPCTL_PCTL_MASK) >> GPR0_PCTL_SINCPCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3930 return Frequency;
3931 }
3932
3933 /* Return SIPI0_CLK frequency */
Clock_Ip_Get_SIPI0_CLK_Frequency(void)3934 static uint32 Clock_Ip_Get_SIPI0_CLK_Frequency(void) {
3935
3936 uint32 Frequency;
3937 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3938 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIPI0PCTL & GPR1_PCTL_SIPI0PCTL_PCTL_MASK) >> GPR1_PCTL_SIPI0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3939 return Frequency;
3940 }
3941
3942 /* Return SIPI1_CLK frequency */
Clock_Ip_Get_SIPI1_CLK_Frequency(void)3943 static uint32 Clock_Ip_Get_SIPI1_CLK_Frequency(void) {
3944
3945 uint32 Frequency;
3946 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/* Selector value */
3947 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIPI1PCTL & GPR1_PCTL_SIPI1PCTL_PCTL_MASK) >> GPR1_PCTL_SIPI1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3948 return Frequency;
3949 }
3950
3951 /* Return SIUL2_0_CLK frequency */
Clock_Ip_Get_SIUL2_0_CLK_Frequency(void)3952 static uint32 Clock_Ip_Get_SIUL2_0_CLK_Frequency(void) {
3953
3954 uint32 Frequency;
3955 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
3956 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->SIUL0PCTL & GPR0_PCTL_SIUL0PCTL_PCTL_MASK) >> GPR0_PCTL_SIUL0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3957 return Frequency;
3958 }
3959
3960 /* Return SIUL2_1_CLK frequency */
Clock_Ip_Get_SIUL2_1_CLK_Frequency(void)3961 static uint32 Clock_Ip_Get_SIUL2_1_CLK_Frequency(void) {
3962
3963 uint32 Frequency;
3964 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();/* Selector value */
3965 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIUL1PCTL & GPR1_PCTL_SIUL1PCTL_PCTL_MASK) >> GPR1_PCTL_SIUL1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3966 return Frequency;
3967 }
3968
3969 /* Return SIUL2_4_CLK frequency */
Clock_Ip_Get_SIUL2_4_CLK_Frequency(void)3970 static uint32 Clock_Ip_Get_SIUL2_4_CLK_Frequency(void) {
3971
3972 uint32 Frequency;
3973 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();
3974 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SIUL4PCTL & GPR4_PCTL_SIUL4PCTL_PCTL_MASK) >> GPR4_PCTL_SIUL4PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3975 return Frequency;
3976 }
3977
3978 /* Return SIUL2_5_CLK frequency */
Clock_Ip_Get_SIUL2_5_CLK_Frequency(void)3979 static uint32 Clock_Ip_Get_SIUL2_5_CLK_Frequency(void) {
3980
3981 uint32 Frequency;
3982 Frequency = Clock_Ip_Get_FIRC_CLK_Frequency();/* Selector value */
3983 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR5_PCTL->SIUL5PCTL & GPR5_PCTL_SIUL5PCTL_PCTL_MASK) >> GPR5_PCTL_SIUL5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
3984 return Frequency;
3985 }
3986
3987
3988 /* Return P4_DSPI_CLK frequency */
Clock_Ip_Get_P4_DSPI_CLK_Frequency(void)3989 static uint32 Clock_Ip_Get_P4_DSPI_CLK_Frequency(void) {
3990
3991 uint32 Frequency;
3992 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
3993 return Frequency;
3994 }
3995
3996 /* Return SPI5_CLK frequency */
Clock_Ip_Get_SPI5_CLK_Frequency(void)3997 static uint32 Clock_Ip_Get_SPI5_CLK_Frequency(void) {
3998
3999 uint32 Frequency;
4000 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
4001 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI5PCTL & GPR4_PCTL_DSPI5PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI5PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
4002 return Frequency;
4003 }
4004
4005 /* Return SPI6_CLK frequency */
Clock_Ip_Get_SPI6_CLK_Frequency(void)4006 static uint32 Clock_Ip_Get_SPI6_CLK_Frequency(void) {
4007
4008 uint32 Frequency;
4009 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_5_CSS & MC_CGM_MUX_5_CSS_SELSTAT_MASK) >> MC_CGM_MUX_5_CSS_SELSTAT_SHIFT)]();/* Selector value */
4010 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI6PCTL & GPR4_PCTL_DSPI6PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI6PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
4011 return Frequency;
4012 }
4013
4014
4015 /* Return SPI7_CLK frequency */
Clock_Ip_Get_SPI7_CLK_Frequency(void)4016 static uint32 Clock_Ip_Get_SPI7_CLK_Frequency(void) {
4017
4018 uint32 Frequency;
4019 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_4_CSS & MC_CGM_MUX_4_CSS_SELSTAT_MASK) >> MC_CGM_MUX_4_CSS_SELSTAT_SHIFT)]();/* Selector value */
4020 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->DSPI7PCTL & GPR4_PCTL_DSPI7PCTL_PCTL_MASK) >> GPR4_PCTL_DSPI7PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
4021 return Frequency;
4022 }
4023
4024 /* Return SRX0_CLK frequency */
Clock_Ip_Get_SRX0_CLK_Frequency(void)4025 static uint32 Clock_Ip_Get_SRX0_CLK_Frequency(void) {
4026
4027 uint32 Frequency;
4028 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_1->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
4029 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
4030 Frequency /= (((IP_MC_CGM_1->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
4031 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SRX0PCTL & GPR1_PCTL_SRX0PCTL_PCTL_MASK) >> GPR1_PCTL_SRX0PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
4032 return Frequency;
4033 }
4034
4035 /* Return SRX1_CLK frequency */
Clock_Ip_Get_SRX1_CLK_Frequency(void)4036 static uint32 Clock_Ip_Get_SRX1_CLK_Frequency(void) {
4037
4038 uint32 Frequency;
4039 Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK) >> MC_CGM_MUX_1_CSS_SELSTAT_SHIFT)]();/* Selector value */
4040 Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> MC_CGM_MUX_1_DC_0_DE_SHIFT)]; /* Divider enable/disable */
4041 Frequency /= (((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DIV_MASK) >> MC_CGM_MUX_1_DC_0_DIV_SHIFT) + 1U); /* Apply divider value */
4042 Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SRX1PCTL & GPR4_PCTL_SRX1PCTL_PCTL_MASK) >> GPR4_PCTL_SRX1PCTL_PCTL_SHIFT)]; /* Apply peripheral clock gate */
4043 return Frequency;
4044 }
4045 /* Return CORE_PLL_REFCLKOUT frequency */
Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void)4046 static uint32 Clock_Ip_Get_CORE_PLL_REFCLKOUT_Frequency(void) {
4047
4048 uint32 Frequency;
4049 Frequency = (((IP_CORE_PLL->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency();/* Selector value */
4050 return Frequency;
4051 }
4052
4053 /* Return PERIPH_PLL_REFCLKOUT frequency */
Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void)4054 static uint32 Clock_Ip_Get_PERIPH_PLL_REFCLKOUT_Frequency(void) {
4055
4056 uint32 Frequency;
4057 Frequency = (((IP_PERIPH_PLL->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency();/* Selector value */
4058 return Frequency;
4059 }
4060
4061
4062 /* Return Px_CLKOUT_SRC_CLK frequency */
Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void)4063 static uint32 Clock_Ip_Get_Px_CLKOUT_SRC_CLK_Frequency(void) {
4064
4065 return Clock_Ip_apfFreqTableCLKOUT_MULTIPLEX[Clock_Ip_u32ClkoutIndex]();/* Selector value */
4066 }
4067
4068
4069 /* Return Px_PSI5_S_UTIL_CLK frequency */
Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void)4070 static uint32 Clock_Ip_Get_Px_PSI5_S_UTIL_CLK_Frequency(void) {
4071
4072 return Clock_Ip_apfFreqTablePSI5_S_UTIL_MULTIPLEX[Clock_Ip_u32PSI5_S_UTILIndex]();/* Selector value */
4073 }
4074
4075 /* Return PLL_VCO frequency */
4076 #define CLOCK_IP_PLL_VCO_MAX_FREQ (2400000000U)
PLL_VCO(const PLLDIG_Type * Base)4077 static uint32 PLL_VCO(const PLLDIG_Type *Base)
4078 {
4079 uint32 Fin;
4080 uint32 Rdiv;
4081 uint32 Mfi;
4082 uint32 Mfn;
4083 uint32 Fout = 0U;
4084 uint32 Var1;
4085 uint32 Var2;
4086 uint32 Var3;
4087 uint32 Var4;
4088 uint32 Var5;
4089 boolean Overflow = FALSE;
4090
4091 Fin = (((Base->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) == 0U) ? Clock_Ip_Get_FIRC_CLK_Frequency() : Clock_Ip_Get_FXOSC_CLK_Frequency(); /* input freq */
4092 Rdiv = ((Base->PLLDV & PLLDIG_PLLDV_RDIV_MASK) >> PLLDIG_PLLDV_RDIV_SHIFT); /* Rdiv */
4093 Mfi = ((Base->PLLDV & PLLDIG_PLLDV_MFI_MASK) >> PLLDIG_PLLDV_MFI_SHIFT); /* Mfi */
4094 Mfn = ((Base->PLLFD & PLLDIG_PLLFD_MFN_MASK) >> PLLDIG_PLLFD_MFN_SHIFT); /* Mfn */
4095
4096
4097 Var1 = Mfi / Rdiv; /* Mfi divided by Rdiv */
4098 Var2 = Mfi - (Var1 * Rdiv); /* Mfi minus Var1 multiplied by Rdiv */
4099 Var3 = (Rdiv << CLOCK_IP_MUL_BY_16384) + (Rdiv << CLOCK_IP_MUL_BY_2048); /* Rdiv multiplied by 18432 */
4100 Var4 = Fin / Var3; /* Fin divide by (Rdiv multiplied by 18432) */
4101 Var5 = Fin - (Var4 * Var3); /* Fin minus Var4 multiplied by (Rdiv mul 18432) */
4102
4103 if (0U != Fin)
4104 {
4105 if (Var1 == ((uint32)(Var1 * Fin) / Fin))
4106 {
4107 Fout = Var1 * Fin; /* Var1 multipied by Fin */
4108 }
4109 else
4110 {
4111 Overflow = TRUE;
4112 }
4113
4114 if ((Var2 == ((uint32)(Fin * Var2) / Fin)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4115 {
4116 Fout += Fin / Rdiv * Var2; /* Fin divided by Rdiv and multiplied by Var2 */
4117 }
4118 else
4119 {
4120 Overflow = TRUE;
4121 }
4122
4123 if (0U != Var4)
4124 {
4125 if ((Mfn == ((uint32)(Var4 * Mfn) / Var4)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4126 {
4127 Fout += Var4 * Mfn; /* Mfn multiplied by Var4 */
4128 }
4129 else
4130 {
4131 Overflow = TRUE;
4132 }
4133 }
4134
4135 if (0U != Mfn)
4136 {
4137 if ((Var5 == ((uint32)(Var5 * Mfn) / Mfn)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout))
4138 {
4139 Fout += Var5 * Mfn / Var3; /* Var5 multiplied by Mfn and divide by (Rdiv mul 18432) */
4140 }
4141 else
4142 {
4143 Overflow = TRUE;
4144 }
4145 }
4146 }
4147
4148 if (TRUE == Overflow)
4149 {
4150 Fout = 0U;
4151 }
4152
4153 return Fout;
4154 }
4155
4156 /* Return LFAST_PLL_VCO frequency */
4157 #define CLOCK_IP_LFAST_PLL_VCO_MAX_FREQ (2400000000U)
LFAST_PLL_VCO(const LFAST_Type * Base)4158 static uint32 LFAST_PLL_VCO(const LFAST_Type *Base)
4159 {
4160 uint32 Fin;
4161 uint32 Prediv;
4162 uint32 PllMode;
4163 uint32 Fbdiv;
4164 uint32 Fout = 0U;
4165 boolean Overflow = FALSE;
4166
4167 /* Input frequency */
4168 if (Base == IP_LFAST_0) {
4169 Fin = Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency();
4170 }
4171 else if (Base == IP_LFAST_1) {
4172 Fin = Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency();
4173 }
4174 else {
4175 Fin = 0U;
4176 }
4177
4178 Prediv = ((Base->PLLCR & LFAST_PLLCR_PREDIV_MASK) >> LFAST_PLLCR_PREDIV_SHIFT) + 1U; /* Prediv */
4179 Fbdiv = ((Base->PLLCR & LFAST_PLLCR_FBDIV_MASK) >> LFAST_PLLCR_FBDIV_SHIFT); /* multiplied */
4180 PllMode = ((Base->PLLCR & LFAST_PLLCR_FDIVEN_MASK) >> LFAST_PLLCR_FDIVEN_SHIFT); /* Pll mode */
4181
4182 if (0U != Fin)
4183 {
4184 if (Fbdiv == ((uint32)(Fin * Fbdiv) / Fin))
4185 {
4186 Fout += ((Fin * Fbdiv )/ Prediv);
4187 }
4188 else
4189 {
4190 Overflow = TRUE;
4191 }
4192
4193 if ((PllMode == ((uint32)(Fin * PllMode) / Fin)) && (CLOCK_IP_LFAST_PLL_VCO_MAX_FREQ >= Fout))
4194 {
4195 if(((Fin / Prediv) > ((Fin * PllMode)/(2U*Prediv))) && (Fout < (Fout + (Fin/Prediv))))
4196 {
4197 /*Fout += (Fin/Prediv) when PllMode = 0 and Fout += (Fin/(2*Prediv)) when PllMode = 1*/
4198 Fout += (Fin/Prediv) - ((Fin * PllMode)/(2U*Prediv));
4199 }
4200 else
4201 {
4202 Overflow = TRUE;
4203 }
4204 }
4205 else
4206 {
4207 Overflow = TRUE;
4208 }
4209 }
4210
4211 if ((1U != ((Base->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT)) || (TRUE == Overflow))
4212 {
4213 Fout = 0U;
4214 }
4215
4216 return Fout;
4217 }
4218
4219 /* Return DFS_OUTPUT frequency */
DFS_OUTPUT(const DFS_Type * Base,uint32 Channel,uint32 Fin)4220 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin)
4221 {
4222 uint32 Mfi;
4223 uint32 Mfn;
4224 uint32 Divider;
4225 uint32 DividerResult;
4226 uint32 DividerModulo;
4227 uint32 Fout = 0U;
4228 boolean Overflow = FALSE;
4229
4230 Mfi = ((Base->DVPORT[Channel] & DFS_DVPORT_MFI_MASK) >> DFS_DVPORT_MFI_SHIFT); /* Mfi */
4231 Mfn = ((Base->DVPORT[Channel] & DFS_DVPORT_MFN_MASK) >> DFS_DVPORT_MFN_SHIFT); /* Mfn */
4232
4233 Divider = ((Mfi << CLOCK_IP_MUL_BY_32) + (Mfi << CLOCK_IP_MUL_BY_4) + Mfn); /* mfi multiplied by 36 add mfn */
4234 DividerResult = (Divider != 0U) ? (Fin / Divider) : 0U; /* Fin divide by Divider */
4235 DividerModulo = Fin - (Divider * DividerResult); /* Fin minus DividerResult multiplied by Divider */
4236
4237 if (Divider != 0U)
4238 {
4239 if ((DividerResult << CLOCK_IP_MUL_BY_16) <= ((DividerResult << CLOCK_IP_MUL_BY_16) + (DividerResult << CLOCK_IP_MUL_BY_2)))
4240 {
4241 Fout += (DividerResult << CLOCK_IP_MUL_BY_16) + (DividerResult << CLOCK_IP_MUL_BY_2);
4242 }
4243 else
4244 {
4245 Overflow = TRUE;
4246 }
4247
4248 if (Fout <= (Fout + (((DividerModulo << CLOCK_IP_MUL_BY_16) + (DividerModulo << CLOCK_IP_MUL_BY_2)) / Divider)))
4249 {
4250 Fout += ((DividerModulo << CLOCK_IP_MUL_BY_16) + (DividerModulo << CLOCK_IP_MUL_BY_2)) / Divider;
4251 }
4252 else
4253 {
4254 Overflow = TRUE;
4255 }
4256 }
4257
4258 if (TRUE == Overflow)
4259 {
4260 Fout = 0U;
4261 }
4262
4263 return Fout;
4264 }
4265
4266 /* Get external frequency */
Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName,uint32 Frequency)4267 void Clock_Ip_SetExternalOscillatorFrequency(Clock_Ip_NameType ExtOscName, uint32 Frequency)
4268 {
4269 (void)ExtOscName;
4270 Clock_Ip_u32Fxosc = Frequency;
4271 }
4272
4273 /* Return LFAST0_PLL_CLK_ frequency */
Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void)4274 static uint32 Clock_Ip_Get_LFAST0_PLL_CLK_Frequency(void)
4275 {
4276 return (((IP_LFAST_0->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAST_PLL_VCO(IP_LFAST_0) : 0U;
4277 }
4278 /* Return LFAST0_PLL_CLK_ frequency */
Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void)4279 static uint32 Clock_Ip_Get_LFAST1_PLL_CLK_Frequency(void)
4280 {
4281 return (((IP_LFAST_1->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAST_PLL_VCO(IP_LFAST_1) : 0U;
4282 }
4283 /*==================================================================================================
4284 * GLOBAL FUNCTIONS
4285 ==================================================================================================*/
4286
4287 /* Return frequency value */
Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)4288 uint32 Clock_Ip_GetFreq(Clock_Ip_NameType ClockName)
4289 {
4290 return Clock_Ip_apfFreqTable[ClockName]();
4291 }
4292
4293 /* Clock stop section code */
4294 #define MCU_STOP_SEC_CODE
4295 #include "Mcu_MemMap.h"
4296
4297 #endif /* #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON)) */
4298
4299 /* Clock start section code */
4300 #define MCU_START_SEC_CODE
4301 #include "Mcu_MemMap.h"
4302
4303 /* Set frequency value for External Signal */
Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName,uint32 Frequency)4304 void Clock_Ip_SetExternalSignalFrequency(Clock_Ip_NameType SignalName, uint32 Frequency)
4305 {
4306 #if (defined(CLOCK_IP_GET_FREQUENCY_API) && (CLOCK_IP_GET_FREQUENCY_API == STD_ON))
4307 uint32 Index;
4308 for (Index = 0U; Index < CLOCK_IP_EXT_SIGNALS_NO; Index++)
4309 {
4310 if (SignalName == Clock_Ip_axExtSignalFreqEntries[Index].Name)
4311 {
4312 Clock_Ip_axExtSignalFreqEntries[Index].Frequency = Frequency;
4313 break;
4314 }
4315 }
4316 #else
4317 (void)SignalName;
4318 (void)Frequency;
4319 #endif
4320 }
4321
4322 /* Clock stop section code */
4323 #define MCU_STOP_SEC_CODE
4324 #include "Mcu_MemMap.h"
4325
4326
4327 #endif /* (CLOCK_IP_PLATFORM_SPECIFIC) */
4328
4329
4330 #ifdef __cplusplus
4331 }
4332 #endif
4333
4334 /** @} */
4335
4336
