MUX_7_DC_0 (reference) in projects: hal_nxp-3.6.0

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Searched refs:MUX_7_DC_0 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	1687 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> … in Clock_Ip_Get_GTM_CLK_Frequency() 1688 …Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHI… in Clock_Ip_Get_GTM_CLK_Frequency() 2992 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_GTM_CLK_Frequency() 2993 …Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHI… in Clock_Ip_Get_P0_GTM_CLK_Frequency() 3002 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency() 3003 …Frequency /= (((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHI… in Clock_Ip_Get_P0_GTM_NOC_CLK_Frequency() 3012 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_GTM_TS_CLK_Frequency() 3013 …Frequency /= ((((IP_MC_CGM_0->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SH… in Clock_Ip_Get_P0_GTM_TS_CLK_Frequency() 3256 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency() 3257 …Frequency /= (((IP_MC_CGM_1->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHI… in Clock_Ip_Get_ETH0_RX_MII_CLK_Frequency() [all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Frequency.c	2838 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_EMAC_RX_CLK_Frequency() 2839 …Frequency /= (((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT… in Clock_Ip_Get_EMAC_RX_CLK_Frequency() 3709 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_GMAC0_RX_CLK_Frequency() 3710 …Frequency /= (((IP_MC_CGM->MUX_7_DC_0 & MC_CGM_MUX_7_DC_0_DIV_MASK) >> MC_CGM_MUX_7_DC_0_DIV_SHIFT… in Clock_Ip_Get_GMAC0_RX_CLK_Frequency()
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
D	S32K344_MC_CGM.h	`124 …__IO uint32_t MUX_7_DC_0; /**< Clock Mux 7 Divider 0 Control Register, offs… member`
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`141 …__IO uint32_t MUX_7_DC_0; /**< Clock Mux 7 Divider 0 Control Register, offs… member`

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