Searched refs:MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (Results 1 – 4 of 4) sorted by relevance
2016 …((IP_MC_CGM_6->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_DDR_CLK_Frequency()2026 …((IP_MC_CGM_0->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P0_SYS_CLK_Frequency()2034 …((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P1_SYS_CLK_Frequency()2042 …((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P1_SYS_DIV2_CLK_Frequency()2051 …((IP_MC_CGM_1->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P1_SYS_DIV4_CLK_Frequency()2060 …((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P2_SYS_CLK_Frequency()2069 …((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P2_SYS_DIV2_CLK_Frequency()2078 …((IP_MC_CGM_2->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P2_SYS_DIV4_CLK_Frequency()2087 …((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_P3_SYS_CLK_Frequency()2095 …((IP_MC_CGM_3->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)]();/*… in Clock_Ip_Get_CE_SYS_DIV2_CLK_Frequency()[all …]
275 #define MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (24U) macro277 …_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)) & MC…
400 #define MC_CGM_MUX_0_CSS_SELSTAT_SHIFT (24U) macro402 …_CSS_SELSTAT(x) (((uint32_t)(((uint32_t)(x)) << MC_CGM_MUX_0_CSS_SELSTAT_SHIFT)) & MC…
1928 …if (((IP_MC_CGM->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK) >> MC_CGM_MUX_0_CSS_SELSTAT_SHIFT) != … in Clock_Ip_Get_SCS_CLK_Frequency()
