Searched refs:IP_GPR1_PCTL (Results 1 – 2 of 2) sorted by relevance
97 #define IP_GPR1_PCTL ((GPR1_PCTL_Type *)IP_GPR1_PCTL_BASE) macro101 #define IP_GPR1_PCTL_BASE_PTRS { IP_GPR1_PCTL }
1748 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN3PCTL & GPR1_PCTL_LIN3PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN3_CLK_Frequency()1758 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN4PCTL & GPR1_PCTL_LIN4PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN4_CLK_Frequency()1768 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->LIN5PCTL & GPR1_PCTL_LIN5PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_LIN5_CLK_Frequency()1923 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI2PCTL & GPR1_PCTL_DSPI2PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SPI2_CLK_Frequency()1932 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI3PCTL & GPR1_PCTL_DSPI3PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SPI3_CLK_Frequency()1941 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->DSPI4PCTL & GPR1_PCTL_DSPI4PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SPI4_CLK_Frequency()2402 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_1_MASK) >… in Clock_Ip_Get_DMACRC1_CLK_Frequency()2443 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_2_MASK) >… in Clock_Ip_Get_DMAMUX1_CLK_Frequency()2577 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->EDMA1PCTL & GPR1_PCTL_EDMA1PCTL_PCTL_0_MASK) >… in Clock_Ip_Get_EDMA1_CLK_Frequency()2624 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->ENET0PCTL & GPR1_PCTL_ENET0PCTL_PCTL_MASK) >> … in Clock_Ip_Get_ENET0_CLK_Frequency()[all …]
