Searched refs:IP_DDR_PLL (Results 1 – 3 of 3) sorted by relevance
98 #define IP_DDR_PLL ((PLLDIG_Type *)IP_DDR_PLL_BASE) macro106 #define IP_PLLDIG_BASE_PTRS { IP_CORE_PLL, IP_DDR_PLL, IP_PERIPH_PLL }
1404 … if (Clock_Ip_u32DdrPllChecksum != (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD)) in Clock_Ip_Get_DDRPLL_CLK_Frequency()1406 … Clock_Ip_u32DdrPllChecksum = (IP_DDR_PLL->PLLCLKMUX ^ IP_DDR_PLL->PLLDV ^ IP_DDR_PLL->PLLFD); in Clock_Ip_Get_DDRPLL_CLK_Frequency()1407 Clock_Ip_u32DdrPllFreq = PLL_VCO(IP_DDR_PLL); in Clock_Ip_Get_DDRPLL_CLK_Frequency()1409 …return (((IP_DDR_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Clock_I… in Clock_Ip_Get_DDRPLL_CLK_Frequency()1602 …Frequency &= Clock_Ip_au32EnableDivider[((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLL… in Clock_Ip_Get_DDRPLL_PHI0_Frequency()1603 …Frequency /= (((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT) + … in Clock_Ip_Get_DDRPLL_PHI0_Frequency()
2912 IP_DDR_PLL,
