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Searched refs:DMA1_ITRIG_EN0_ID (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_inputmux_connections.h43 #define DMA1_ITRIG_EN0_ID 0x7A0U macro
448 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
449 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
450 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
451 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
452 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
453 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
454 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
455 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
456 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_inputmux_connections.h43 #define DMA1_ITRIG_EN0_ID 0x7A0U macro
448 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
449 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
450 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
451 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
452 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
453 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
454 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
455 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
456 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_inputmux_connections.h45 #define DMA1_ITRIG_EN0_ID 0x7A0U macro
560 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
561 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
562 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
563 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
564 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
565 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
566 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
567 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
568 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_inputmux_connections.h45 #define DMA1_ITRIG_EN0_ID 0x7A0U macro
560 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
561 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
562 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
563 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
564 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
565 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
566 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
567 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
568 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_inputmux_connections.h45 #define DMA1_ITRIG_EN0_ID 0x7A0U macro
560 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
561 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
562 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
563 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
564 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
565 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
566 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
567 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
568 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
[all …]