1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2019, NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_INPUTMUX_CONNECTIONS_ 10 #define _FSL_INPUTMUX_CONNECTIONS_ 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 /* Component ID definition, used by tools. */ 16 #ifndef FSL_COMPONENT_ID 17 #define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" 18 #endif 19 20 /*! 21 * @addtogroup inputmux_driver 22 * @{ 23 */ 24 25 /*! @brief Periphinmux IDs */ 26 #define SCT0_PMUX_ID 0x00U 27 #define PINTSEL_PMUX_ID 0x100U 28 #define DSP_INT_PMUX_ID 0x140U 29 #define DMA0_ITRIG_PMUX_ID 0x200U 30 #define DMA0_OTRIG_PMUX_ID 0x300U 31 #define DMA0_CHMUX_SEL0_ID 0x320U 32 #define DMA1_ITRIG_PMUX_ID 0x400U 33 #define DMA1_OTRIG_PMUX_ID 0x500U 34 #define DMA1_CHMUX_SEL0_ID 0x520U 35 #define CT32BIT0_CAP_PMUX_ID 0x600U 36 #define CT32BIT1_CAP_PMUX_ID 0x610U 37 #define CT32BIT2_CAP_PMUX_ID 0x620U 38 #define CT32BIT3_CAP_PMUX_ID 0x630U 39 #define CT32BIT4_CAP_PMUX_ID 0x640U 40 #define FREQMEAS_PMUX_ID 0x700U 41 #define SMART_DMA_PMUX_ID 0x720U 42 #define DMA0_REQ_ENA0_ID 0x740U 43 #define DMA1_REQ_ENA0_ID 0x760U 44 #define DMA0_ITRIG_EN0_ID 0x780U 45 #define DMA1_ITRIG_EN0_ID 0x7A0U 46 47 #define ENA_SHIFT 5U 48 #define PMUX_SHIFT 20U 49 #define CHMUX_AVL_SHIFT 31U 50 #define CHMUX_OFF_SHIFT 19U 51 #define CHMUX_VAL_SHIFT 17U 52 53 /*! @brief INPUTMUX connections type */ 54 typedef enum _inputmux_connection_t 55 { 56 /*!< SCT INMUX. */ 57 kINPUTMUX_Sct0PinInp0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT), 58 kINPUTMUX_Sct0PinInp1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT), 59 kINPUTMUX_Sct0PinInp2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT), 60 kINPUTMUX_Sct0PinInp3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT), 61 kINPUTMUX_Sct0PinInp4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT), 62 kINPUTMUX_Sct0PinInp5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT), 63 kINPUTMUX_Sct0PinInp6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT), 64 kINPUTMUX_Sct0PinInp7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT), 65 kINPUTMUX_Ctimer0Mat0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT), 66 kINPUTMUX_Ctimer1Mat0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT), 67 kINPUTMUX_Ctimer2Mat0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT), 68 kINPUTMUX_Ctimer3Mat0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT), 69 kINPUTMUX_Ctimer4Mat0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT), 70 kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT), 71 kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT), 72 kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT), 73 kINPUTMUX_Cmp0OutToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT), 74 kINPUTMUX_SharedI2s0SclkToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT), 75 kINPUTMUX_SharedI2s1SclkToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT), 76 kINPUTMUX_SharedI2s0WsToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT), 77 kINPUTMUX_SharedI2s1WsToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT), 78 kINPUTMUX_MclkToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT), 79 kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT), 80 kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT), 81 82 /*!< Pin Interrupt. */ 83 kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 84 kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 85 kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 86 kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 87 kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 88 kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 89 kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 90 kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 91 kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 92 kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 93 kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 94 kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 95 kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 96 kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 97 kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 98 kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 99 kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 100 kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 101 kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 102 kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 103 kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 104 kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 105 kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 106 kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 107 kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 108 kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 109 kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 110 kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 111 kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 112 kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 113 kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 114 kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 115 kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 116 kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 117 kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 118 kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 119 kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 120 kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 121 kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 122 kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 123 kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 124 kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 125 kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 126 kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 127 kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 128 kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 129 kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 130 kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 131 kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 132 kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 133 kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 134 kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 135 kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 136 kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 137 kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 138 kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 139 kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 140 kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 141 kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 142 kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 143 kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 144 kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 145 kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 146 kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), 147 148 /*!< DSP Interrupt. */ 149 kINPUTMUX_Flexcomm0ToDspInterrupt = 0U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 150 kINPUTMUX_Flexcomm1ToDspInterrupt = 1U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 151 kINPUTMUX_Flexcomm2ToDspInterrupt = 2U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 152 kINPUTMUX_Flexcomm3ToDspInterrupt = 3U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 153 kINPUTMUX_Flexcomm4ToDspInterrupt = 4U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 154 kINPUTMUX_Flexcomm5ToDspInterrupt = 5U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 155 kINPUTMUX_Flexcomm6ToDspInterrupt = 6U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 156 kINPUTMUX_Flexcomm7ToDspInterrupt = 7U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 157 kINPUTMUX_Flexcomm14ToDspInterrupt = 8U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 158 kINPUTMUX_Flexcomm16ToDspInterrupt = 9U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 159 kINPUTMUX_GpioInt0ToDspInterrupt = 10U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 160 kINPUTMUX_GpioInt1ToDspInterrupt = 11U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 161 kINPUTMUX_GpioInt2ToDspInterrupt = 12U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 162 kINPUTMUX_GpioInt3ToDspInterrupt = 13U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 163 kINPUTMUX_GpioInt4ToDspInterrupt = 14U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 164 kINPUTMUX_GpioInt5ToDspInterrupt = 15U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 165 kINPUTMUX_GpioInt6ToDspInterrupt = 16U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 166 kINPUTMUX_GpioInt7ToDspInterrupt = 17U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 167 kINPUTMUX_NsHsGpioInt0ToDspInterrupt = 18U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 168 kINPUTMUX_NsHsGpioInt1ToDspInterrupt = 19U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 169 kINPUTMUX_Wdt1ToDspInterrupt = 20U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 170 kINPUTMUX_Dmac0ToDspInterrupt = 21U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 171 kINPUTMUX_Dmac1ToDspInterrupt = 22U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 172 kINPUTMUX_MuBToDspInterrupt = 23U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 173 kINPUTMUX_Utick0ToDspInterrupt = 24U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 174 kINPUTMUX_Mrt0ToDspInterrupt = 25U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 175 kINPUTMUX_OsEventTimerToDspInterrupt = 26U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 176 kINPUTMUX_Ctimer0ToDspInterrupt = 27U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 177 kINPUTMUX_Ctimer1ToDspInterrupt = 28U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 178 kINPUTMUX_Ctimer2ToDspInterrupt = 29U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 179 kINPUTMUX_Ctimer3ToDspInterrupt = 30U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 180 kINPUTMUX_Ctimer4ToDspInterrupt = 31U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 181 kINPUTMUX_RtcToDspInterrupt = 32U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 182 kINPUTMUX_I3c0ToDspInterrupt = 33U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 183 kINPUTMUX_I3c1ToDspInterrupt = 34U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 184 kINPUTMUX_Dmic0ToDspInterrupt = 35U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 185 kINPUTMUX_HwvadToDspInterrupt = 36U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 186 kINPUTMUX_LcdifToDspInterrupt = 37U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 187 kINPUTMUX_GpuToDspInterrupt = 38U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 188 kINPUTMUX_SmartDmaToDspInterrupt = 39U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 189 kINPUTMUX_FlexioToDspInterrupt = 40U + (DSP_INT_PMUX_ID << PMUX_SHIFT), 190 191 /*!< Frequency measure. */ 192 kINPUTMUX_XtalinToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 193 kINPUTMUX_Fro12mToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 194 kINPUTMUX_Fro192mToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 195 kINPUTMUX_LposcToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 196 kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 197 kINPUTMUX_MainSysClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 198 kINPUTMUX_FreqmeGpioClkToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 199 kINPUTMUX_ClockOutToFreqmeas = 11U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), 200 201 /*!< SMARTDMA input mux. */ 202 kINPUTMUX_GpioPort0Pin0ToSmartDmaInput = 0U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 203 kINPUTMUX_GpioPort0Pin1ToSmartDmaInput = 1U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 204 kINPUTMUX_GpioPort0Pin2ToSmartDmaInput = 2U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 205 kINPUTMUX_GpioPort0Pin3ToSmartDmaInput = 3U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 206 kINPUTMUX_GpioPort0Pin4ToSmartDmaInput = 4U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 207 kINPUTMUX_GpioPort0Pin5ToSmartDmaInput = 5U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 208 kINPUTMUX_GpioPort0Pin6ToSmartDmaInput = 6U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 209 kINPUTMUX_GpioPort0Pin7ToSmartDmaInput = 7U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 210 kINPUTMUX_GpioPort1Pin0ToSmartDmaInput = 8U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 211 kINPUTMUX_GpioPort1Pin1ToSmartDmaInput = 9U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 212 kINPUTMUX_GpioPort1Pin2ToSmartDmaInput = 10U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 213 kINPUTMUX_GpioPort1Pin3ToSmartDmaInput = 11U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 214 kINPUTMUX_GpioPort1Pin4ToSmartDmaInput = 12U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 215 kINPUTMUX_GpioPort1Pin5ToSmartDmaInput = 13U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 216 kINPUTMUX_GpioPort1Pin6ToSmartDmaInput = 14U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 217 kINPUTMUX_GpioPort1Pin7ToSmartDmaInput = 15U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 218 kINPUTMUX_Flexcomm0IrqToSmartDmaInput = 16U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 219 kINPUTMUX_Flexcomm1IrqToSmartDmaInput = 17U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 220 kINPUTMUX_Flexcomm2IrqToSmartDmaInput = 18U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 221 kINPUTMUX_Flexcomm3IrqToSmartDmaInput = 19U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 222 kINPUTMUX_Flexcomm4IrqToSmartDmaInput = 20U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 223 kINPUTMUX_Flexcomm5IrqToSmartDmaInput = 21U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 224 kINPUTMUX_Flexcomm6IrqToSmartDmaInput = 22U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 225 kINPUTMUX_Flexcomm7IrqToSmartDmaInput = 23U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 226 kINPUTMUX_Flexcomm14IrqToSmartDmaInput = 24U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 227 kINPUTMUX_Flexcomm16IrqToSmartDmaInput = 25U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 228 kINPUTMUX_I3c0IrqToSmartDmaInput = 26U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 229 kINPUTMUX_I3c1IrqToSmartDmaInput = 27U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 230 kINPUTMUX_FlexioIrqToSmartDmaInput = 28U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 231 kINPUTMUX_GpioInt0Irq0ToSmartDmaInput = 29U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 232 kINPUTMUX_GpioInt0Irq1ToSmartDmaInput = 30U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 233 kINPUTMUX_GpioInt0Irq2ToSmartDmaInput = 31U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 234 kINPUTMUX_GpioInt0Irq3ToSmartDmaInput = 32U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 235 kINPUTMUX_GpioInt0Irq4ToSmartDmaInput = 33U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 236 kINPUTMUX_GpioInt0Irq5ToSmartDmaInput = 34U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 237 kINPUTMUX_GpioInt0Irq6ToSmartDmaInput = 35U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 238 kINPUTMUX_GpioInt0Irq7ToSmartDmaInput = 36U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 239 kINPUTMUX_NsGpioHsIrq0ToSmartDmaInput = 37U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 240 kINPUTMUX_NsGpioHsIrq1ToSmartDmaInput = 38U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 241 kINPUTMUX_Sct0IrqToSmartDmaInput = 39U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 242 kINPUTMUX_Ctimer0IrqToSmartDmaInput = 40U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 243 kINPUTMUX_Ctimer1IrqToSmartDmaInput = 41U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 244 kINPUTMUX_Ctimer2IrqToSmartDmaInput = 42U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 245 kINPUTMUX_Ctimer3IrqToSmartDmaInput = 43U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 246 kINPUTMUX_Ctimer4IrqToSmartDmaInput = 44U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 247 kINPUTMUX_Utick0IrqToSmartDmaInput = 45U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 248 kINPUTMUX_Mrt0IrqToSmartDmaInput = 46U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 249 kINPUTMUX_RtcLite0IrqToSmartDmaInput = 47U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 250 kINPUTMUX_OsEventIrqToSmartDmaInput = 48U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 251 kINPUTMUX_Wdt0IrqToSmartDmaInput = 49U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 252 kINPUTMUX_Wdt1IrqToSmartDmaInput = 50U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 253 kINPUTMUX_Adc0IrqToSmartDmaInput = 51U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 254 kINPUTMUX_AcmpIrqToSmartDmaInput = 52U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 255 kINPUTMUX_Dmic0ToSmartDmaInput = 53U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 256 kINPUTMUX_HwvadToSmartDmaInput = 54U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 257 kINPUTMUX_Sdio0IrqToSmartDmaInput = 55U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 258 kINPUTMUX_Sdio1IrqToSmartDmaInput = 56U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 259 kINPUTMUX_Usb0IrqToSmartDmaInput = 57U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 260 kINPUTMUX_Usb0NeedClkToSmartDmaInput = 58U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 261 kINPUTMUX_LcdifIrqToSmartDmaInput = 59U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 262 kINPUTMUX_GpuIrqToSmartDmaInput = 60U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 263 kINPUTMUX_Dma0IrqToSmartDmaInput = 61U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 264 kINPUTMUX_Dma1IrqToSmartDmaInput = 62U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 265 kINPUTMUX_PowerquadIrqToSmartDmaInput = 63U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 266 kINPUTMUX_FlexspiIrqToSmartDmaInput = 64U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 267 kINPUTMUX_DspTieExpstate1ToSmartDmaInput = 65U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 268 kINPUTMUX_SctOut8ToSmartDmaInput = 66U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 269 kINPUTMUX_SctOut9ToSmartDmaInput = 67U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 270 kINPUTMUX_T4Mat3ToSmartDmaInput = 68U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 271 kINPUTMUX_T4Mat2ToSmartDmaInput = 69U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 272 kINPUTMUX_T3Mat3ToSmartDmaInput = 70U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 273 kINPUTMUX_T3Mat2ToSmartDmaInput = 71U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 274 kINPUTMUX_ArmTxevToSmartDmaInput = 72U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 275 kINPUTMUX_GpiointBmatchToSmartDmaInput = 73U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 276 kINPUTMUX_MipiIrqToSmartDmaInput = 74U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 277 kINPUTMUX_UsbFsToggleToSmartDmaInput = 75U + (SMART_DMA_PMUX_ID << PMUX_SHIFT), 278 279 /*!< CTmier0 capture input mux. */ 280 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 281 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 282 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 283 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 284 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 285 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 286 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 287 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 288 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 289 kINPUTMUX_CtInp9ToTimer0CaptureChannels = 9U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 290 kINPUTMUX_CtInp10ToTimer0CaptureChannels = 10U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 291 kINPUTMUX_CtInp11ToTimer0CaptureChannels = 11U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 292 kINPUTMUX_CtInp12ToTimer0CaptureChannels = 12U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 293 kINPUTMUX_CtInp13ToTimer0CaptureChannels = 13U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 294 kINPUTMUX_CtInp14ToTimer0CaptureChannels = 14U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 295 kINPUTMUX_CtInp15ToTimer0CaptureChannels = 15U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 296 kINPUTMUX_SharedI2s0WsToTimer0CaptureChannels = 16U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 297 kINPUTMUX_SharedI2s1WsToTimer0CaptureChannels = 17U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 298 kINPUTMUX_Usb1FrameToggleToTimer0CaptureChannels = 18U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT), 299 300 /*!< CTmier1 capture input mux. */ 301 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 302 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 303 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 304 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 305 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 306 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 307 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 308 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 309 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 310 kINPUTMUX_CtInp9ToTimer1CaptureChannels = 9U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 311 kINPUTMUX_CtInp10ToTimer1CaptureChannels = 10U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 312 kINPUTMUX_CtInp11ToTimer1CaptureChannels = 11U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 313 kINPUTMUX_CtInp12ToTimer1CaptureChannels = 12U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 314 kINPUTMUX_CtInp13ToTimer1CaptureChannels = 13U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 315 kINPUTMUX_CtInp14ToTimer1CaptureChannels = 14U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 316 kINPUTMUX_CtInp15ToTimer1CaptureChannels = 15U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 317 kINPUTMUX_SharedI2s0WsToTimer1CaptureChannels = 16U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 318 kINPUTMUX_SharedI2s1WsToTimer1CaptureChannels = 17U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 319 kINPUTMUX_Usb1FrameToggleToTimer1CaptureChannels = 18U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT), 320 321 /*!< CTmier2 capture input mux. */ 322 kINPUTMUX_CtInp0ToTimer2CaptureChannels = 0U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 323 kINPUTMUX_CtInp1ToTimer2CaptureChannels = 1U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 324 kINPUTMUX_CtInp2ToTimer2CaptureChannels = 2U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 325 kINPUTMUX_CtInp3ToTimer2CaptureChannels = 3U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 326 kINPUTMUX_CtInp4ToTimer2CaptureChannels = 4U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 327 kINPUTMUX_CtInp5ToTimer2CaptureChannels = 5U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 328 kINPUTMUX_CtInp6ToTimer2CaptureChannels = 6U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 329 kINPUTMUX_CtInp7ToTimer2CaptureChannels = 7U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 330 kINPUTMUX_CtInp8ToTimer2CaptureChannels = 8U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 331 kINPUTMUX_CtInp9ToTimer2CaptureChannels = 9U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 332 kINPUTMUX_CtInp10ToTimer2CaptureChannels = 10U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 333 kINPUTMUX_CtInp11ToTimer2CaptureChannels = 11U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 334 kINPUTMUX_CtInp12ToTimer2CaptureChannels = 12U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 335 kINPUTMUX_CtInp13ToTimer2CaptureChannels = 13U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 336 kINPUTMUX_CtInp14ToTimer2CaptureChannels = 14U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 337 kINPUTMUX_CtInp15ToTimer2CaptureChannels = 15U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 338 kINPUTMUX_SharedI2s0WsToTimer2CaptureChannels = 16U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 339 kINPUTMUX_SharedI2s1WsToTimer2CaptureChannels = 17U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 340 kINPUTMUX_Usb1FrameToggleToTimer2CaptureChannels = 18U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT), 341 342 /*!< CTmier3 capture input mux. */ 343 kINPUTMUX_CtInp0ToTimer3CaptureChannels = 0U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 344 kINPUTMUX_CtInp1ToTimer3CaptureChannels = 1U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 345 kINPUTMUX_CtInp2ToTimer3CaptureChannels = 2U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 346 kINPUTMUX_CtInp3ToTimer3CaptureChannels = 3U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 347 kINPUTMUX_CtInp4ToTimer3CaptureChannels = 4U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 348 kINPUTMUX_CtInp5ToTimer3CaptureChannels = 5U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 349 kINPUTMUX_CtInp6ToTimer3CaptureChannels = 6U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 350 kINPUTMUX_CtInp7ToTimer3CaptureChannels = 7U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 351 kINPUTMUX_CtInp8ToTimer3CaptureChannels = 8U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 352 kINPUTMUX_CtInp9ToTimer3CaptureChannels = 9U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 353 kINPUTMUX_CtInp10ToTimer3CaptureChannels = 10U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 354 kINPUTMUX_CtInp11ToTimer3CaptureChannels = 11U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 355 kINPUTMUX_CtInp12ToTimer3CaptureChannels = 12U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 356 kINPUTMUX_CtInp13ToTimer3CaptureChannels = 13U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 357 kINPUTMUX_CtInp14ToTimer3CaptureChannels = 14U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 358 kINPUTMUX_CtInp15ToTimer3CaptureChannels = 15U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 359 kINPUTMUX_SharedI2s0WsToTimer3CaptureChannels = 16U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 360 kINPUTMUX_SharedI2s1WsToTimer3CaptureChannels = 17U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 361 kINPUTMUX_Usb1FrameToggleToTimer3CaptureChannels = 18U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT), 362 363 /*!< CTmier4 capture input mux. */ 364 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 365 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 366 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 367 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 368 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 369 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 370 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 371 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 372 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 373 kINPUTMUX_CtInp9ToTimer4CaptureChannels = 9U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 374 kINPUTMUX_CtInp10ToTimer4CaptureChannels = 10U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 375 kINPUTMUX_CtInp11ToTimer4CaptureChannels = 11U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 376 kINPUTMUX_CtInp12ToTimer4CaptureChannels = 12U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 377 kINPUTMUX_CtInp13ToTimer4CaptureChannels = 13U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 378 kINPUTMUX_CtInp14ToTimer4CaptureChannels = 14U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 379 kINPUTMUX_CtInp15ToTimer4CaptureChannels = 15U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 380 kINPUTMUX_SharedI2s0WsToTimer4CaptureChannels = 16U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 381 kINPUTMUX_SharedI2s1WsToTimer4CaptureChannels = 17U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 382 kINPUTMUX_Usb1FrameToggleToTimer4CaptureChannels = 18U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT), 383 384 /*!< DMA0 ITRIG. */ 385 kINPUTMUX_GpioInt0ToDma0 = 0U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 386 kINPUTMUX_GpioInt1ToDma0 = 1U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 387 kINPUTMUX_GpioInt2ToDma0 = 2U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 388 kINPUTMUX_GpioInt3ToDma0 = 3U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 389 kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 390 kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 391 kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 392 kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 393 kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 394 kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 395 kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 396 kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 397 kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 398 kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 399 kINPUTMUX_Dma0TrigOutAToDma0 = 14U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 400 kINPUTMUX_Dma0TrigOutBToDma0 = 15U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 401 kINPUTMUX_Dma0TrigOutCToDma0 = 16U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 402 kINPUTMUX_Dma0TrigOutDToDma0 = 17U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 403 kINPUTMUX_SctDma0ToDma0 = 18U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 404 kINPUTMUX_SctDma1ToDma0 = 19U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 405 kINPUTMUX_HashCryptOutToDma0 = 20U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 406 kINPUTMUX_AcmpToDma0 = 21U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 407 kINPUTMUX_Flexspi0RxToDma0 = 22U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 408 kINPUTMUX_Flexspi0TxToDma0 = 23U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 409 kINPUTMUX_AdcToDma0 = 24U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 410 kINPUTMUX_Flexspi1RxToDma0 = 25U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 411 kINPUTMUX_Flexspi1TxToDma0 = 26U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT), 412 413 /*!< DMA1 ITRIG. */ 414 kINPUTMUX_GpioInt0ToDma1 = 0U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 415 kINPUTMUX_GpioInt1ToDma1 = 1U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 416 kINPUTMUX_GpioInt2ToDma1 = 2U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 417 kINPUTMUX_GpioInt3ToDma1 = 3U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 418 kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 419 kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 420 kINPUTMUX_Ctimer1M0ToDma1 = 6U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 421 kINPUTMUX_Ctimer1M1ToDma1 = 7U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 422 kINPUTMUX_Ctimer2M0ToDma1 = 8U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 423 kINPUTMUX_Ctimer2M1ToDma1 = 9U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 424 kINPUTMUX_Ctimer3M0ToDma1 = 10U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 425 kINPUTMUX_Ctimer3M1ToDma1 = 11U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 426 kINPUTMUX_Ctimer4M0ToDma1 = 12U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 427 kINPUTMUX_Ctimer4M1ToDma1 = 13U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 428 kINPUTMUX_Dma0TrigOutAToDma1 = 14U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 429 kINPUTMUX_Dma0TrigOutBToDma1 = 15U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 430 kINPUTMUX_Dma0TrigOutCToDma1 = 16U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 431 kINPUTMUX_Dma0TrigOutDToDma1 = 17U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 432 kINPUTMUX_SctDma0ToDma1 = 18U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 433 kINPUTMUX_SctDma1ToDma1 = 19U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 434 kINPUTMUX_HashCryptOutToDma1 = 20U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 435 kINPUTMUX_AcmpToDma1 = 21U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 436 kINPUTMUX_Flexspi0RxToDma1 = 22U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 437 kINPUTMUX_Flexspi0TxToDma1 = 23U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 438 kINPUTMUX_AdcToDma1 = 24U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 439 kINPUTMUX_Flexspi1RxToDma1 = 25U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 440 kINPUTMUX_Flexspi1TxToDma1 = 26U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT), 441 442 /*!< DMA0 OTRIG. */ 443 kINPUTMUX_Dma0OtrigChannel0ToTriginChannels = 0U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 444 kINPUTMUX_Dma0OtrigChannel1ToTriginChannels = 1U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 445 kINPUTMUX_Dma0OtrigChannel2ToTriginChannels = 2U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 446 kINPUTMUX_Dma0OtrigChannel3ToTriginChannels = 3U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 447 kINPUTMUX_Dma0OtrigChannel4ToTriginChannels = 4U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 448 kINPUTMUX_Dma0OtrigChannel5ToTriginChannels = 5U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 449 kINPUTMUX_Dma0OtrigChannel6ToTriginChannels = 6U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 450 kINPUTMUX_Dma0OtrigChannel7ToTriginChannels = 7U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 451 kINPUTMUX_Dma0OtrigChannel8ToTriginChannels = 8U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 452 kINPUTMUX_Dma0OtrigChannel9ToTriginChannels = 9U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 453 kINPUTMUX_Dma0OtrigChannel10ToTriginChannels = 10U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 454 kINPUTMUX_Dma0OtrigChannel11ToTriginChannels = 11U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 455 kINPUTMUX_Dma0OtrigChannel12ToTriginChannels = 12U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 456 kINPUTMUX_Dma0OtrigChannel13ToTriginChannels = 13U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 457 kINPUTMUX_Dma0OtrigChannel14ToTriginChannels = 14U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 458 kINPUTMUX_Dma0OtrigChannel15ToTriginChannels = 15U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 459 kINPUTMUX_Dma0OtrigChannel16ToTriginChannels = 16U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 460 kINPUTMUX_Dma0OtrigChannel17ToTriginChannels = 17U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 461 kINPUTMUX_Dma0OtrigChannel18ToTriginChannels = 18U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 462 kINPUTMUX_Dma0OtrigChannel19ToTriginChannels = 19U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 463 kINPUTMUX_Dma0OtrigChannel20ToTriginChannels = 20U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 464 kINPUTMUX_Dma0OtrigChannel21ToTriginChannels = 21U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 465 kINPUTMUX_Dma0OtrigChannel22ToTriginChannels = 22U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 466 kINPUTMUX_Dma0OtrigChannel23ToTriginChannels = 23U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 467 kINPUTMUX_Dma0OtrigChannel24ToTriginChannels = 24U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 468 kINPUTMUX_Dma0OtrigChannel25ToTriginChannels = 25U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 469 kINPUTMUX_Dma0OtrigChannel26ToTriginChannels = 26U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 470 kINPUTMUX_Dma0OtrigChannel27ToTriginChannels = 27U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 471 kINPUTMUX_Dma0OtrigChannel28ToTriginChannels = 28U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 472 kINPUTMUX_Dma0OtrigChannel29ToTriginChannels = 29U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 473 kINPUTMUX_Dma0OtrigChannel30ToTriginChannels = 30U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 474 kINPUTMUX_Dma0OtrigChannel31ToTriginChannels = 31U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 475 kINPUTMUX_Dma0OtrigChannel32ToTriginChannels = 32U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 476 kINPUTMUX_Dma0OtrigChannel33ToTriginChannels = 33U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 477 kINPUTMUX_Dma0OtrigChannel34ToTriginChannels = 34U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 478 kINPUTMUX_Dma0OtrigChannel35ToTriginChannels = 35U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 479 kINPUTMUX_Dma0OtrigChannel36ToTriginChannels = 36U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT), 480 481 /*!< DMA1 OTRIG. */ 482 kINPUTMUX_Dma1OtrigChannel0ToTriginChannels = 0U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 483 kINPUTMUX_Dma1OtrigChannel1ToTriginChannels = 1U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 484 kINPUTMUX_Dma1OtrigChannel2ToTriginChannels = 2U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 485 kINPUTMUX_Dma1OtrigChannel3ToTriginChannels = 3U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 486 kINPUTMUX_Dma1OtrigChannel4ToTriginChannels = 4U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 487 kINPUTMUX_Dma1OtrigChannel5ToTriginChannels = 5U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 488 kINPUTMUX_Dma1OtrigChannel6ToTriginChannels = 6U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 489 kINPUTMUX_Dma1OtrigChannel7ToTriginChannels = 7U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 490 kINPUTMUX_Dma1OtrigChannel8ToTriginChannels = 8U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 491 kINPUTMUX_Dma1OtrigChannel9ToTriginChannels = 9U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 492 kINPUTMUX_Dma1OtrigChannel10ToTriginChannels = 10U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 493 kINPUTMUX_Dma1OtrigChannel11ToTriginChannels = 11U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 494 kINPUTMUX_Dma1OtrigChannel12ToTriginChannels = 12U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 495 kINPUTMUX_Dma1OtrigChannel13ToTriginChannels = 13U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 496 kINPUTMUX_Dma1OtrigChannel14ToTriginChannels = 14U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 497 kINPUTMUX_Dma1OtrigChannel15ToTriginChannels = 15U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 498 kINPUTMUX_Dma1OtrigChannel16ToTriginChannels = 16U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 499 kINPUTMUX_Dma1OtrigChannel17ToTriginChannels = 17U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 500 kINPUTMUX_Dma1OtrigChannel18ToTriginChannels = 18U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 501 kINPUTMUX_Dma1OtrigChannel19ToTriginChannels = 19U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 502 kINPUTMUX_Dma1OtrigChannel20ToTriginChannels = 20U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 503 kINPUTMUX_Dma1OtrigChannel21ToTriginChannels = 21U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 504 kINPUTMUX_Dma1OtrigChannel22ToTriginChannels = 22U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 505 kINPUTMUX_Dma1OtrigChannel23ToTriginChannels = 23U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 506 kINPUTMUX_Dma1OtrigChannel24ToTriginChannels = 24U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 507 kINPUTMUX_Dma1OtrigChannel25ToTriginChannels = 25U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 508 kINPUTMUX_Dma1OtrigChannel26ToTriginChannels = 26U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 509 kINPUTMUX_Dma1OtrigChannel27ToTriginChannels = 27U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 510 kINPUTMUX_Dma1OtrigChannel28ToTriginChannels = 28U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 511 kINPUTMUX_Dma1OtrigChannel29ToTriginChannels = 29U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 512 kINPUTMUX_Dma1OtrigChannel30ToTriginChannels = 30U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 513 kINPUTMUX_Dma1OtrigChannel31ToTriginChannels = 31U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 514 kINPUTMUX_Dma1OtrigChannel32ToTriginChannels = 32U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 515 kINPUTMUX_Dma1OtrigChannel33ToTriginChannels = 33U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 516 kINPUTMUX_Dma1OtrigChannel34ToTriginChannels = 34U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 517 kINPUTMUX_Dma1OtrigChannel35ToTriginChannels = 35U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 518 kINPUTMUX_Dma1OtrigChannel36ToTriginChannels = 36U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT), 519 } inputmux_connection_t; 520 521 /*! @brief INPUTMUX signal enable/disable type */ 522 /* Encode: [31:31]: ChannelMux available flag 523 * [30:19]: ChannelMux register offset 524 * [18:17]: ChannelMux register value 525 * [16: 5]: Signal enable register offset 526 * [ 4: 0]: Signal enable bit location 527 */ 528 typedef enum _inputmux_signal_t 529 { 530 /*!< DMA0 input trigger source enable. */ 531 kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 532 kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 533 kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 534 kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 535 kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 536 kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 537 kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 538 kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 539 kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 540 kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 541 kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 542 kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 543 kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 544 kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 545 kINPUTMUX_Dmac0InputTriggerDma0OutAEna = 14U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 546 kINPUTMUX_Dmac0InputTriggerDma0OutBEna = 15U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 547 kINPUTMUX_Dmac0InputTriggerDma0OutCEna = 16U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 548 kINPUTMUX_Dmac0InputTriggerDma0OutDEna = 17U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 549 kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 18U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 550 kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 19U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 551 kINPUTMUX_Dmac0InputTriggerHashOutEna = 20U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 552 kINPUTMUX_Dmac0InputTriggerAcmpEna = 21U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 553 kINPUTMUX_Dmac0InputTriggerFlexspi0RxEna = 22U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 554 kINPUTMUX_Dmac0InputTriggerFlexspi0TxEna = 23U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 555 kINPUTMUX_Dmac0InputTriggerAdcEna = 24U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 556 kINPUTMUX_Dmac0InputTriggerFlexspi1RxEna = 25U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 557 kINPUTMUX_Dmac0InputTriggerFlexspi1TxEna = 26U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT), 558 559 /*!< DMA1 input trigger source enable. */ 560 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 561 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 562 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 563 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 564 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 565 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 566 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 567 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 568 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 569 kINPUTMUX_Dmac1InputTriggerCtimer2M1Ena = 9U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 570 kINPUTMUX_Dmac1InputTriggerCtimer3M0Ena = 10U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 571 kINPUTMUX_Dmac1InputTriggerCtimer3M1Ena = 11U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 572 kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 12U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 573 kINPUTMUX_Dmac1InputTriggerCtimer4M1Ena = 13U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 574 kINPUTMUX_Dmac1InputTriggerDma1OutAEna = 14U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 575 kINPUTMUX_Dmac1InputTriggerDma1OutBEna = 15U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 576 kINPUTMUX_Dmac1InputTriggerDma1OutCEna = 16U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 577 kINPUTMUX_Dmac1InputTriggerDma1OutDEna = 17U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 578 kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 18U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 579 kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 19U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 580 kINPUTMUX_Dmac1InputTriggerHashOutEna = 20U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 581 kINPUTMUX_Dmac1InputTriggerAcmpEna = 21U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 582 kINPUTMUX_Dmac1InputTriggerFlexspi0RxEna = 22U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 583 kINPUTMUX_Dmac1InputTriggerFlexspi0TxEna = 23U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 584 kINPUTMUX_Dmac1InputTriggerAdcEna = 24U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 585 kINPUTMUX_Dmac1InputTriggerFlexspi1RxEna = 25U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 586 kINPUTMUX_Dmac1InputTriggerFlexspi1TxEna = 26U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT), 587 588 /*!< DMA0 REQ signal. */ 589 kINPUTMUX_Flexcomm0RxToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 590 kINPUTMUX_Flexcomm0TxToDmac0Ch1RequestEna = 1U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 591 kINPUTMUX_Flexcomm1RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 592 kINPUTMUX_Flexcomm1TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 593 kINPUTMUX_Flexcomm2RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 594 kINPUTMUX_Flexcomm2TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 595 kINPUTMUX_Flexcomm3RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 596 kINPUTMUX_Flexcomm3TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 597 kINPUTMUX_Flexcomm4RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 598 kINPUTMUX_Flexcomm4TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 599 kINPUTMUX_Flexcomm5RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 600 kINPUTMUX_Flexcomm5TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 601 kINPUTMUX_Flexcomm6RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 602 kINPUTMUX_Flexcomm6TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 603 kINPUTMUX_Flexcomm7RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 604 kINPUTMUX_Flexcomm7TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 605 kINPUTMUX_Dmic0Ch0ToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 606 (DMA0_CHMUX_SEL0_ID << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 607 kINPUTMUX_Flexcomm8RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 608 (DMA0_CHMUX_SEL0_ID << CHMUX_OFF_SHIFT) + (1U << CHMUX_VAL_SHIFT), 609 kINPUTMUX_Dmic0Ch1ToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 610 ((DMA0_CHMUX_SEL0_ID + 4) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 611 kINPUTMUX_Flexcomm8TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 612 ((DMA0_CHMUX_SEL0_ID + 4) << CHMUX_OFF_SHIFT) + 613 (1U << CHMUX_VAL_SHIFT), 614 kINPUTMUX_Dmic0Ch2ToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 615 ((DMA0_CHMUX_SEL0_ID + 8) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 616 kINPUTMUX_Flexcomm9RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 617 ((DMA0_CHMUX_SEL0_ID + 8) << CHMUX_OFF_SHIFT) + 618 (1U << CHMUX_VAL_SHIFT), 619 kINPUTMUX_Dmic0Ch3ToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 620 ((DMA0_CHMUX_SEL0_ID + 12) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 621 kINPUTMUX_Flexcomm9TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 622 ((DMA0_CHMUX_SEL0_ID + 12) << CHMUX_OFF_SHIFT) + 623 (1U << CHMUX_VAL_SHIFT), 624 kINPUTMUX_Dmic0Ch4ToDmac0Ch20RequestEna = 20U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 625 ((DMA0_CHMUX_SEL0_ID + 16) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 626 kINPUTMUX_Flexcomm10RxToDmac0Ch20RequestEna = 20U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 627 ((DMA0_CHMUX_SEL0_ID + 16) << CHMUX_OFF_SHIFT) + 628 (1U << CHMUX_VAL_SHIFT), 629 kINPUTMUX_Dmic0Ch5ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 630 ((DMA0_CHMUX_SEL0_ID + 20) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 631 kINPUTMUX_Flexcomm10TxToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 632 ((DMA0_CHMUX_SEL0_ID + 20) << CHMUX_OFF_SHIFT) + 633 (1U << CHMUX_VAL_SHIFT), 634 kINPUTMUX_Dmic0Ch6ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 635 ((DMA0_CHMUX_SEL0_ID + 24) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 636 kINPUTMUX_Flexcomm13RxToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 637 ((DMA0_CHMUX_SEL0_ID + 24) << CHMUX_OFF_SHIFT) + 638 (1U << CHMUX_VAL_SHIFT), 639 kINPUTMUX_Dmic0Ch7ToDmac0Ch23RequestEna = 23U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 640 ((DMA0_CHMUX_SEL0_ID + 28) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 641 kINPUTMUX_Flexcomm13TxToDmac0Ch23RequestEna = 23U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 642 ((DMA0_CHMUX_SEL0_ID + 28) << CHMUX_OFF_SHIFT) + 643 (1U << CHMUX_VAL_SHIFT), 644 kINPUTMUX_I3c0RxToDmac0Ch24RequestEna = 24U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 645 kINPUTMUX_I3c0TxToDmac0Ch25RequestEna = 25U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 646 kINPUTMUX_Flexcomm14RxToDmac0Ch26RequestEna = 26U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 647 kINPUTMUX_Flexcomm14TxToDmac0Ch27RequestEna = 27U + (DMA0_REQ_ENA0_ID << ENA_SHIFT), 648 kINPUTMUX_Flexcomm16RxToDmac0Ch28RequestEna = 28U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 649 ((DMA0_CHMUX_SEL0_ID + 32) << CHMUX_OFF_SHIFT) + 650 (0U << CHMUX_VAL_SHIFT), 651 kINPUTMUX_Flexcomm16TxToDmac0Ch29RequestEna = 29U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 652 ((DMA0_CHMUX_SEL0_ID + 36) << CHMUX_OFF_SHIFT) + 653 (0U << CHMUX_VAL_SHIFT), 654 kINPUTMUX_I3c1RxToDmac0Ch30RequestEna = 30U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 655 ((DMA0_CHMUX_SEL0_ID + 40) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 656 kINPUTMUX_I3c1TxToDmac0Ch31RequestEna = 31U + (DMA0_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 657 ((DMA0_CHMUX_SEL0_ID + 44) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 658 kINPUTMUX_Flexcomm11RxToDmac0Ch32RequestEna = 0U + ((DMA0_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 659 ((DMA0_CHMUX_SEL0_ID + 48) << CHMUX_OFF_SHIFT) + 660 (1U << CHMUX_VAL_SHIFT), 661 kINPUTMUX_Flexcomm11TxToDmac0Ch33RequestEna = 1U + ((DMA0_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 662 ((DMA0_CHMUX_SEL0_ID + 52) << CHMUX_OFF_SHIFT) + 663 (1U << CHMUX_VAL_SHIFT), 664 kINPUTMUX_Flexcomm12RxToDmac0Ch34RequestEna = 2U + ((DMA0_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 665 ((DMA0_CHMUX_SEL0_ID + 56) << CHMUX_OFF_SHIFT) + 666 (1U << CHMUX_VAL_SHIFT), 667 kINPUTMUX_Flexcomm12TxToDmac0Ch35RequestEna = 3U + ((DMA0_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 668 ((DMA0_CHMUX_SEL0_ID + 60) << CHMUX_OFF_SHIFT) + 669 (1U << CHMUX_VAL_SHIFT), 670 kINPUTMUX_HashCryptToDmac0Ch36RequestEna = 4U + ((DMA0_REQ_ENA0_ID + 4) << ENA_SHIFT), 671 672 /*!< DMA1 REQ signal. */ 673 kINPUTMUX_Flexcomm0RxToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 674 kINPUTMUX_Flexcomm0TxToDmac1Ch1RequestEna = 1U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 675 kINPUTMUX_Flexcomm1RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 676 kINPUTMUX_Flexcomm1TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 677 kINPUTMUX_Flexcomm2RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 678 kINPUTMUX_Flexcomm2TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 679 kINPUTMUX_Flexcomm3RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 680 kINPUTMUX_Flexcomm3TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 681 kINPUTMUX_Flexcomm4RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 682 kINPUTMUX_Flexcomm4TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 683 kINPUTMUX_Flexcomm5RxToDmac1Ch10RequestEna = 10U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 684 kINPUTMUX_Flexcomm5TxToDmac1Ch11RequestEna = 11U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 685 kINPUTMUX_Flexcomm6RxToDmac1Ch12RequestEna = 12U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 686 kINPUTMUX_Flexcomm6TxToDmac1Ch13RequestEna = 13U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 687 kINPUTMUX_Flexcomm7RxToDmac1Ch14RequestEna = 14U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 688 kINPUTMUX_Flexcomm7TxToDmac1Ch15RequestEna = 15U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 689 kINPUTMUX_Dmic0Ch0ToDmac1Ch16RequestEna = 16U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 690 (DMA1_CHMUX_SEL0_ID << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 691 kINPUTMUX_Flexcomm8RxToDmac1Ch16RequestEna = 16U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 692 (DMA1_CHMUX_SEL0_ID << CHMUX_OFF_SHIFT) + (1U << CHMUX_VAL_SHIFT), 693 kINPUTMUX_Dmic0Ch1ToDmac1Ch17RequestEna = 17U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 694 ((DMA1_CHMUX_SEL0_ID + 4) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 695 kINPUTMUX_Flexcomm8TxToDmac1Ch17RequestEna = 17U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 696 ((DMA1_CHMUX_SEL0_ID + 4) << CHMUX_OFF_SHIFT) + 697 (1U << CHMUX_VAL_SHIFT), 698 kINPUTMUX_Dmic0Ch2ToDmac1Ch18RequestEna = 18U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 699 ((DMA1_CHMUX_SEL0_ID + 8) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 700 kINPUTMUX_Flexcomm9RxToDmac1Ch18RequestEna = 18U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 701 ((DMA1_CHMUX_SEL0_ID + 8) << CHMUX_OFF_SHIFT) + 702 (1U << CHMUX_VAL_SHIFT), 703 kINPUTMUX_Dmic0Ch3ToDmac1Ch19RequestEna = 19U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 704 ((DMA1_CHMUX_SEL0_ID + 12) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 705 kINPUTMUX_Flexcomm9TxToDmac1Ch19RequestEna = 19U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 706 ((DMA1_CHMUX_SEL0_ID + 12) << CHMUX_OFF_SHIFT) + 707 (1U << CHMUX_VAL_SHIFT), 708 kINPUTMUX_Dmic0Ch4ToDmac1Ch20RequestEna = 20U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 709 ((DMA1_CHMUX_SEL0_ID + 16) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 710 kINPUTMUX_Flexcomm10RxToDmac1Ch20RequestEna = 20U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 711 ((DMA1_CHMUX_SEL0_ID + 16) << CHMUX_OFF_SHIFT) + 712 (1U << CHMUX_VAL_SHIFT), 713 kINPUTMUX_Dmic0Ch5ToDmac1Ch21RequestEna = 21U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 714 ((DMA1_CHMUX_SEL0_ID + 20) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 715 kINPUTMUX_Flexcomm10TxToDmac1Ch21RequestEna = 21U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 716 ((DMA1_CHMUX_SEL0_ID + 20) << CHMUX_OFF_SHIFT) + 717 (1U << CHMUX_VAL_SHIFT), 718 kINPUTMUX_Dmic0Ch6ToDmac1Ch22RequestEna = 22U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 719 ((DMA1_CHMUX_SEL0_ID + 24) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 720 kINPUTMUX_Flexcomm13RxToDmac1Ch22RequestEna = 22U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 721 ((DMA1_CHMUX_SEL0_ID + 24) << CHMUX_OFF_SHIFT) + 722 (1U << CHMUX_VAL_SHIFT), 723 kINPUTMUX_Dmic0Ch7ToDmac1Ch23RequestEna = 23U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 724 ((DMA1_CHMUX_SEL0_ID + 28) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 725 kINPUTMUX_Flexcomm13TxToDmac1Ch23RequestEna = 23U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 726 ((DMA1_CHMUX_SEL0_ID + 28) << CHMUX_OFF_SHIFT) + 727 (1U << CHMUX_VAL_SHIFT), 728 kINPUTMUX_I3c0RxToDmac1Ch24RequestEna = 24U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 729 kINPUTMUX_I3c0TxToDmac1Ch25RequestEna = 25U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 730 kINPUTMUX_Flexcomm14RxToDmac1Ch26RequestEna = 26U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 731 kINPUTMUX_Flexcomm14TxToDmac1Ch27RequestEna = 27U + (DMA1_REQ_ENA0_ID << ENA_SHIFT), 732 kINPUTMUX_Flexcomm16RxToDmac1Ch28RequestEna = 28U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 733 ((DMA1_CHMUX_SEL0_ID + 32) << CHMUX_OFF_SHIFT) + 734 (0U << CHMUX_VAL_SHIFT), 735 kINPUTMUX_Flexcomm16TxToDmac1Ch29RequestEna = 29U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 736 ((DMA1_CHMUX_SEL0_ID + 36) << CHMUX_OFF_SHIFT) + 737 (0U << CHMUX_VAL_SHIFT), 738 kINPUTMUX_I3c1RxToDmac1Ch30RequestEna = 30U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 739 ((DMA1_CHMUX_SEL0_ID + 40) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 740 kINPUTMUX_I3c1TxToDmac1Ch31RequestEna = 31U + (DMA1_REQ_ENA0_ID << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 741 ((DMA1_CHMUX_SEL0_ID + 44) << CHMUX_OFF_SHIFT) + (0U << CHMUX_VAL_SHIFT), 742 kINPUTMUX_Flexcomm11RxToDmac1Ch32RequestEna = 0U + ((DMA1_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 743 ((DMA1_CHMUX_SEL0_ID + 48) << CHMUX_OFF_SHIFT) + 744 (1U << CHMUX_VAL_SHIFT), 745 kINPUTMUX_Flexcomm11TxToDmac1Ch33RequestEna = 1U + ((DMA1_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 746 ((DMA1_CHMUX_SEL0_ID + 52) << CHMUX_OFF_SHIFT) + 747 (1U << CHMUX_VAL_SHIFT), 748 kINPUTMUX_Flexcomm12RxToDmac1Ch34RequestEna = 2U + ((DMA1_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 749 ((DMA1_CHMUX_SEL0_ID + 56) << CHMUX_OFF_SHIFT) + 750 (1U << CHMUX_VAL_SHIFT), 751 kINPUTMUX_Flexcomm12TxToDmac1Ch35RequestEna = 3U + ((DMA1_REQ_ENA0_ID + 4) << ENA_SHIFT) + (1U << CHMUX_AVL_SHIFT) + 752 ((DMA1_CHMUX_SEL0_ID + 60) << CHMUX_OFF_SHIFT) + 753 (1U << CHMUX_VAL_SHIFT), 754 kINPUTMUX_HashCryptToDmac1Ch36RequestEna = 4U + ((DMA1_REQ_ENA0_ID + 4) << ENA_SHIFT), 755 } inputmux_signal_t; 756 757 /*@}*/ 758 759 #endif /* _FSL_INPUTMUX_CONNECTIONS_ */ 760
