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Searched refs:DMA1_IRQn (Results 1 – 25 of 76) sorted by relevance

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/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K116_COMMON.h163 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K118_COMMON.h163 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K144_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K142_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K144W_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K142W_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K146_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
DS32K148_COMMON.h167 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h137 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
993 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h106 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
1550 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h115 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
1559 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h133 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
2507 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h133 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
2511 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h88 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
2415 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h134 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
2531 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h79 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
4025 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h136 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
3294 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h136 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
3298 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
1541 DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn \
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
1541 DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn \
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h81 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
1541 DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn \
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h136 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
2533 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h142 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
3300 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h152 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ enumerator
3314 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h128 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ enumerator
4651 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…

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