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Searched refs:CMP1_IRQn (Results 1 – 25 of 35) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h173 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1053 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h173 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1057 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h108 CMP1_IRQn = 21, /**< CMP1 interrupt */ enumerator
971 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h106 CMP1_IRQn = 21, /**< CMP1 interrupt */ enumerator
962 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h174 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1070 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h106 CMP1_IRQn = 21, /**< CMP1 interrupt */ enumerator
1749 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h176 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1072 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h176 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1072 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h176 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1072 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h111 CMP1_IRQn = 21, /**< CMP1 interrupt */ enumerator
1226 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h111 CMP1_IRQn = 21, /**< CMP1 interrupt */ enumerator
1225 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h182 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1078 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h192 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
1088 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h168 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
2010 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h185 CMP1_IRQn = 41, /**< Comparator 1 */ enumerator
1269 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h185 CMP1_IRQn = 41, /**< Comparator 1 */ enumerator
1269 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h127 CMP1_IRQn = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */ enumerator
2061 CMP0_IRQn, CMP1_IRQn \
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h127 CMP1_IRQn = 49, /**< CMP1 interrupt (INTMUX source IRQ17) */ enumerator
2061 CMP0_IRQn, CMP1_IRQn \
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h168 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
3008 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h168 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
3012 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h194 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
4905 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h191 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
6742 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h186 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
6771 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h199 CMP1_IRQn = 41, /**< CMP1 interrupt */ enumerator
6784 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h169 CMP1_IRQn = 41, /**< Comparator 1 */ enumerator
7216 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }

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