CLOCK_IP_DISABLED (reference) in projects: hal_nxp-3.6.0

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Searched refs:CLOCK_IP_DISABLED (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
D	Clock_Ip_Frequency.c	`87 #define CLOCK_IP_DISABLED 0U macro 291 static const uint32 Clock_Ip_u32EnableClock[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; 292 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; 958 const uint32 EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; in get_CLKOUT0_CLK_Frequency()`
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Frequency.c	`90 #define CLOCK_IP_DISABLED 0U macro 1644 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; 1645 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};`
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	`100 #define CLOCK_IP_DISABLED 0U macro 470 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; 471 static const uint32 Clock_Ip_u32EnableGate[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED};`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
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