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Searched refs:CH_CFG1 (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CANXL_MRU.h79 …__IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0… member
DS32Z2_SMU_MRU.h79 …__IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0… member
DS32Z2_RTU_MRU.h79 …__IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0… member
DS32Z2_CE_MRU.h79 …__IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0… member
/hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c70 base->CHXCONFIG[0u].CH_CFG1 |= CANXL_MRU_CH_CFG1_MBIC3_MASK; in Canexcel_GetControllerMRU()
995 uint32 tmp = base->CHXCONFIG[0u].CH_CFG1; in Canexcel_Ip_MruIRQHandler()