| /hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/ |
| D | Qspi_Ip_HyperflashRegs.h | 35 #define QSPI_IP_HF_SR_ESTAT(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_ESTAT_SHIFT))&…
39 #define QSPI_IP_HF_SR_SLSB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_SLSB_SHIFT))&Q…
43 #define QSPI_IP_HF_SR_PSSB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_PSSB_SHIFT))&Q…
47 #define QSPI_IP_HF_SR_WBASB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_WBASB_SHIFT))&…
51 #define QSPI_IP_HF_SR_PSB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_PSB_SHIFT))&QS…
55 #define QSPI_IP_HF_SR_ESB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_ESB_SHIFT))&QS…
59 #define QSPI_IP_HF_SR_ESSB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_ESSB_SHIFT))&Q…
63 #define QSPI_IP_HF_SR_DRB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_DRB_SHIFT))&QS…
67 #define QSPI_IP_HF_SR_CRCSSB(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_SR_CRCSSB_SHIFT))…
73 #define QSPI_IP_HF_xVCR_BL(x) (((uint16)(((uint16)(x)) << QSPI_IP_HF_xVCR_BL_SHIFT))&…
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| D | Qspi_Ip_Types.h | 127 #define QSPI_IP_LUT_INVALID (uint16)0xFFFFU
129 #define QSPI_IP_LUT_SEQ_END (uint16)0x0U
218 typedef uint16 Qspi_Ip_InstrOpType;
325 …uint16 sizes[QSPI_IP_AHB_BUFFERS]; /*!< List of buffer sizes */
486 …uint16 statusRegInitReadLut; /*!< Command used to read the status register during initializati…
487 …uint16 statusRegReadLut; /*!< Command used to read the status register …
488 …uint16 statusRegWriteLut; /*!< Command used to write the status register …
489 …uint16 writeEnableSRLut; /*!< Write enable command used before writing to status register …
490 …uint16 writeEnableLut; /*!< Write enable command used before write or erase operations …
508 uint16 eraseLut; /*!< Lut index for erase command */
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/ |
| D | Power_Ip_AEC_Types.h | 88 #define AEC_AE_RSTGEN_CFG_REGS_OTP_ENABLE_U16 ((uint16)(0x0001))
89 #define AEC_AE_RSTGEN_CFG_REGS_OTP_DISABLE_U16 ((uint16)(0x0000))
90 #define AEC_AE_RSTGEN_CFG_CANPHY_ENABLE_U16 ((uint16)(0x0002))
91 #define AEC_AE_RSTGEN_CFG_CANPHY_DISABLE_U16 ((uint16)(0x0000))
92 #define AEC_AE_RSTGEN_CFG_LINPHY_HP_ENABLE_U16 ((uint16)(0x0004))
93 #define AEC_AE_RSTGEN_CFG_LINPHY_HP_DISABLE_U16 ((uint16)(0x0000))
94 #define AEC_AE_RSTGEN_CFG_LINPHY_LP_ENABLE_U16 ((uint16)(0x0008))
95 #define AEC_AE_RSTGEN_CFG_LINPHY_LP_DISABLE_U16 ((uint16)(0x0000))
96 #define AEC_AE_RSTGEN_CFG_GDU_ENABLE_U16 ((uint16)(0x0010))
97 #define AEC_AE_RSTGEN_CFG_GDU_DISABLE_U16 ((uint16)(0x0000))
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/include/ |
| D | Netc_Eth_Ip_Types.h | 285 …uint16 length; /*!< The length field specifies the effective number of bytes in the data bu…
286 uint16 index; /*!< The index refers to an entry location within a table. */
287 uint16 commandConfig; /*!< Set of flags. */
311 …const uint16 TxTimestampID; /*!< UNUSED! Only used for the system with address spaces on 64 bits…
312 const uint16 RESERVED_0; /*!< UNUSED! */
314 const uint16 RESERVED_2; /*!< UNUSED! */
315 const uint16 FlagsAndStatus; /*!< Buffer descriptor configuration for a normal descriptor. */
324 const uint16 TxTimestampID; /*!< Transmit Timestamp Identifier. */
325 const uint16 RESERVED_1; /*!< UNUSED! */
326 const uint16 HostReason; /*!< Host Reason 0: Regular forwarded frame
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| D | Netc_Eth_Ip.h | 162 uint16 *buffId);
222 uint16 NumBuffers);
249 uint16 NumBuffers,
250 const uint16 BufferLength[],
251 uint16 *buffId);
337 uint16* BuffListSize);
478 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetRxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 P…
492 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SetTxCoalescingThresholds(uint8 CtrlIdx, uint8 RingIdx, uint16 P…
504 void Netc_Eth_Ip_ManagementFrame(uint8 CtrlIdx, uint16 BuffIdx, const Netc_Eth_Ip_TxTimestampInfoTy…
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/ |
| D | Adc_Sar_Ip_Types.h | 286 typedef void Adc_Sar_Ip_ChanNotificationType(const uint16 PhysicalChanId);
299 typedef void Adc_Sar_Ip_WdgNotificationType(const uint16 ChanIdx, const uint8 Flags);
360 uint16 LowThreshold; /*!< Lower threshold */
361 uint16 HighThreshold; /*!< Upper threshold */
378 uint16 ConvData; /*!< Conversion Data */
404 uint16 AdcSTAW0RHighVal; /*!< Adc STAW0R threshold high value */
405 uint16 AdcSTAW0RLowVal; /*!< Adc STAW0R threshold low value */
408 uint16 AdcSTAW1RLowVal; /*!< Adc STAW1R threshold low value */
411 uint16 AdcSTAW1ARHighVal; /*!< Adc STAW1AR threshold high value */
412 uint16 AdcSTAW1ARLowVal; /*!< Adc STAW1AR threshold low value */
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Spi/include/ |
| D | Spi_Ip_Types.h | 152 uint16 PushrCmd; /**< PUSHR CMD Fifo register which contains CS and continuos mode. */
171 uint16 DmaFastPushrCmd; /**< PUSHR CMD Fifo register which contains CS and continuos mode. */
172 …uint16 DmaFastPushrCmdLast; /**< PUSHR CMD Fifo register which contains CS and disable continuos…
185 uint16 Length; /**< Number of bytes to be sent */
228 uint16 RxIndex; /**< Store current Rx index to receive data in Rx buffer */
229 uint16 TxIndex; /**< Store current Tx index to transmit data in Tx buffer */
230 …uint16 ExpectedFifoReads; /**< Store number of frames needs to be receive for current transfer …
231 …uint16 ExpectedFifoWrites; /**< Store number of frames needs to be transmit for current transfer…
232 …uint16 ExpectedCmdFifoWrites; /**< Store number of frames needs to be transmit for current trans…
233 uint16 PushrCmd; /**< PUSHR CMD Fifo register which contains CS and continuos mode. */
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/include/ |
| D | Gmac_Ip.h | 194 uint16 * BuffId);
275 uint16 NumBuffers,
276 const uint16 BufferLength[],
277 uint16 *buffId);
417 uint16 *Data,
434 uint16 Data,
452 uint16 PhyReg,
453 uint16 *Data,
471 uint16 PhyReg,
472 uint16 Data,
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| D | Gmac_Ip_Types.h | 547 uint16 GateControlDepth;
548 uint16 ReleaseAdvanceTime;
549 uint16 HoldAdvanceTime;
568 uint16 BufferLen; /*!< Length of each individual buffer in a pool */
569 uint16 RingSize; /*!< Buffer descriptors number. */
586 uint16 BufferLen; /*!< Length of each individual buffer in a pool */
587 uint16 RingSize; /*!< Buffer descriptors number. */
600 uint16 Length; /*!< Length of the data buffer */
611 … uint16 secondsHi; /*!< The 16 most significant bits of the 48 bit seconds part of the time. */
697 …uint16 PktLen; /*!< Byte length of the received packet that was transferred to…
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| D | Gmac_Ip_Hw_Access.h | 94 uint16 PhysReg;
95 uint16 MmdAddr;
97 uint16 FrameData;
215 static inline uint16 GMAC_ReadManagementFrameData(const GMAC_Type * Base) in GMAC_ReadManagementFrameData()
217 return (uint16)(Base->MAC_MDIO_DATA & GMAC_MAC_MDIO_DATA_GD_MASK); in GMAC_ReadManagementFrameData()
409 uint16 * VlanTag);
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| /hal_nxp-3.5.0/s32/soc/s32k344/include/ |
| D | Emios_Mcl_Ip_Cfg_Defines.h | 94 #define EMIOS_CH_0 ((uint16)0U)
95 #define EMIOS_CH_8 ((uint16)8U)
96 #define EMIOS_CH_16 ((uint16)16U)
97 #define EMIOS_CH_22 ((uint16)22U)
98 #define EMIOS_CH_23 ((uint16)23U)
118 #define MCL_EMIOS_LOGIC_CH0 (uint16)((0U << 8U) + EMIOS_CH_23)
119 #define MCL_EMIOS_LOGIC_CH1 (uint16)((1U << 8U) + EMIOS_CH_23)
120 #define MCL_EMIOS_LOGIC_CH2 (uint16)((2U << 8U) + EMIOS_CH_23)
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| /hal_nxp-3.5.0/s32/drivers/s32ze/EthSwt_NETC/include/ |
| D | Netc_EthSwt_Ip_Types.h | 159 uint16 FID; /*!< Filtering ID */
177 uint16 FID; /*!< Filtering ID */
402 …uint16 ReqBuffLength; /*!< Table Request data buffer length field of…
403 …uint16 RspBuffLength; /*!< Table Response data buffer length field o…
933 …uint16 EgressFrmModificationDataLength; /*!< Egress Frame …
1072 uint16 FrmModificationDataBytes; /*!< Frame Modification Data Bytes */
1086 uint16 OuterVlanVID; /*!< Outer VLAN VID */
1234 uint16 KeyePrecedence; /*!< Precedence field */
1235 uint16 keyeFrmAttributeFlags; /*!< Frame Attribute Flags field */
1236 …uint16 KeyeFrmAttributeFlagsMask; /*!< Frame Attribute Flags Mask field …
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/ |
| D | Emios_Pwm_Ip_Types.h | 182 typedef uint16 Emios_Pwm_Ip_InternalClkPsType;
380 uint16 InternalPs;
382 uint16 InternalPsAlt;
410 uint16 PeriodCount;
412 uint16 DutyCycle;
414 uint16 PhaseShift;
416 uint16 DeadTime;
418 uint16 TriggerPosition;
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/ |
| D | Spi_Ip.c | 145 #define SPI_IP_DMA_MAX_ITER_CNT_U16 ((uint16)0x7FFFu)
151 #define SPI_IP_CTARE_DTCP_MAX_U16 (uint16) 2047u
216 uint16 Iter,
235 uint16 NumberOfReads,
240 uint16 NumberOfWrites,
245 uint16 NumberOfReads,
254 uint16 NumberOfWrites,
261 uint16 Length
268 uint16 Length
286 uint16 NumberOfReads; in Spi_Ip_TransferProcess()
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Icu/include/ |
| D | Emios_Icu_Ip_Types.h | 320 typedef void (*eMios_Icu_Ip_CallbackType)(uint16 callbackParam1, boolean callbackParam2);
323 typedef void (*eMios_Icu_Ip_LogicChStateCbType)(uint16 logicChannel, uint8 mask, boolean set);
383 uint16 callbackParam;
392 uint16 eMios_Icu_Ip_aBufferSize;
394 uint16 eMios_Icu_Ip_aBufferNotify;
396 uint16 eMios_Icu_Ip_aNotifyCount;
398 uint16 eMios_Icu_Ip_aBufferIndex;
416 uint16 edgeNumbers;
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Fls/src/ |
| D | Qspi_Ip_Hyperflash.c | 441 uint16 lut in Qspi_Ip_HyperflashPatchReadCommand()
463 uint16 lut, in Qspi_Ip_HyperflashPatchRunReadCommand()
483 static uint16 Qspi_Ip_HyperflashGetConfigurationValue(const Qspi_Ip_HyperFlashConfigType *config) in Qspi_Ip_HyperflashGetConfigurationValue()
485 uint16 regVal; in Qspi_Ip_HyperflashGetConfigurationValue()
490 regVal = (uint16)((uint16)QSPI_IP_HF_xVCR_BL((uint8)0x3U) | in Qspi_Ip_HyperflashGetConfigurationValue()
491 (uint16)QSPI_IP_HF_xVCR_RWDS(RWDSLowOnDualError) | in Qspi_Ip_HyperflashGetConfigurationValue()
492 (uint16)QSPI_IP_HF_xVCR_RL((uint8)config->readLatency) | in Qspi_Ip_HyperflashGetConfigurationValue()
493 (uint16)QSPI_IP_HF_xVCR_PSM((uint8)config->paramSectorMap) | in Qspi_Ip_HyperflashGetConfigurationValue()
494 (uint16)QSPI_IP_HF_xVCR_SSR(secureRegionUnlocked) | in Qspi_Ip_HyperflashGetConfigurationValue()
495 (uint16)QSPI_IP_HF_xVCR_FRZ(1U) | in Qspi_Ip_HyperflashGetConfigurationValue()
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| /hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/include/ |
| D | Eth_GeneralTypes.h | 363 typedef uint16 Eth_FrameType;
398 uint16 secondsHi; /**< @brief 16 bit MSB of the 48 bits Seconds part of the time */
514 uint16 VlanId;
516 uint16 HashValue;
536 …uint16 VlanIdFilter; /**< @brief Specifies the VLAN address 0..4094 that should be …
542 …uint16 ReTaggingVlanId; /**< @brief Specifies the VLAN address 0..4094 which shall be used fo…
543 …uint16 DoubleTaggingVlanId; /**< @brief Specifies the VLAN address 0..4094 which shall be use…
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Port/include/ |
| D | Siul2_Port_Ip.h | 205 uint16 pin,
220 uint16 pin,
243 uint16 pin,
272 uint16 pin,
285 uint16 pin);
299 uint16 pin);
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Dio/src/ |
| D | Siul2_Dio_Ip.c | 137 static inline uint16 Siul2_Dio_Ip_Rev_Bit_16(uint16 value);
144 static inline uint16 Siul2_Dio_Ip_Rev_Bit_16(uint16 value) in Siul2_Dio_Ip_Rev_Bit_16()
147 uint16 ret = 0U; in Siul2_Dio_Ip_Rev_Bit_16()
151 … ret |= (uint16)((((value >> i) & 1U) << (15U - i)) | (((value << i) & 0x8000U) >> (15U - i))); in Siul2_Dio_Ip_Rev_Bit_16()
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Port/include/ |
| D | Siul2_Port_Ip.h | 230 uint16 pin,
245 uint16 pin,
268 uint16 pin,
297 uint16 pin,
310 uint16 pin);
324 uint16 pin);
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Dio/src/ |
| D | Siul2_Dio_Ip.c | 140 static inline uint16 Siul2_Dio_Ip_Rev_Bit_16(uint16 value);
147 static inline uint16 Siul2_Dio_Ip_Rev_Bit_16(uint16 value) in Siul2_Dio_Ip_Rev_Bit_16()
150 uint16 ret = 0U; in Siul2_Dio_Ip_Rev_Bit_16()
154 … ret |= (uint16)((((value >> i) & 1U) << (15U - i)) | (((value << i) & 0x8000U) >> (15U - i))); in Siul2_Dio_Ip_Rev_Bit_16()
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| /hal_nxp-3.5.0/s32/soc/s32z27/include/ |
| D | Siul2_Port_Ip_Defines.h | 188 #define PORT_SIUL2_0_IMCRS_IDX_END_U16 ((uint16)89)
189 #define PORT_SIUL2_1_IMCRS_IDX_END_U16 ((uint16)209)
190 #define PORT_SIUL2_3_IMCRS_IDX_END_U16 ((uint16)23)
191 #define PORT_SIUL2_4_IMCRS_IDX_END_U16 ((uint16)371)
192 #define PORT_SIUL2_5_IMCRS_IDX_END_U16 ((uint16)474)
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/ |
| D | Power_Ip_AEC.c | 176 TmpAe = (uint16)(TmpAe & (uint16)(~AEC_AE_RSTGEN_CFG_RSTGEN_CFG_MASK)); in Power_Ip_AEC_Reset_Config()
177 TmpAe = (uint16)(TmpAe | (uint16)(ConfigPtr->Rstgencfg)); in Power_Ip_AEC_Reset_Config()
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| /hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip.c | 166 #define GMAC_GCRA_LOWER_BTR ((uint16)0U)
167 #define GMAC_GCRA_UPPER_BTR ((uint16)1U)
168 #define GMAC_GCRA_LOWER_CTR ((uint16)2U)
169 #define GMAC_GCRA_UPPER_CTR ((uint16)3U)
170 #define GMAC_GCRA_TER ((uint16)4U)
171 #define GMAC_GCRA_LLR ((uint16)5U)
290 uint16 AddrGateList,
312 uint16 NumQueues,
370 uint16 CurrTimeSecHi; in Gmac_Ip_ReadTimeStampInfo()
383 CurrTimeSecHi = (uint16)(Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS); in Gmac_Ip_ReadTimeStampInfo()
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| /hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/src/ |
| D | Netc_Eth_Ip.c | 284 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold);
411 … Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][currBDIdx].TxTimeStampID = (uint16)0xFFFFU; in Netc_Eth_Ip_InitTxBD()
412 … Netc_Eth_Ip_TxTimestampInfoBuff[ctrlIndex][currBDIdx].TxBuffId = (uint16)0xFFFFU; in Netc_Eth_Ip_InitTxBD()
606 …Status = (Netc_Eth_Ip_StatusType)((uint16)(((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.… in Netc_Eth_Ip_SendMsgFromVsiToPsi()
705 …Status = (Netc_Eth_Ip_StatusType)((uint16)(((Netc_Eth_Ip_VsiBaseType*) netcSIsBase[VsiId])->MSGSR.… in Netc_Eth_Ip_WaitVsiToPsiMsgTransmission()
903 static uint8 Netc_Eth_Ip_CoalescingTxPacketsConversion (uint16 PacketsThreshold) in Netc_Eth_Ip_CoalescingTxPacketsConversion()
905 uint16 RegVal = 1U; in Netc_Eth_Ip_CoalescingTxPacketsConversion()
1323 uint16 *buffId) in Netc_Eth_Ip_GetTxBuff()
1362 buff->length = (uint16)(Netc_Eth_Ip_apxState[ctrlIndex]->TxBufferLength[ring]); in Netc_Eth_Ip_GetTxBuff()
1378 *buffId = (uint16)(currProducerIdx); in Netc_Eth_Ip_GetTxBuff()
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