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/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/gpio/
Dfsl_gpio.h197 static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask) in GPIO_SecurePrivilegeLock() argument
199 base->LOCK |= GPIO_FIT_REG(mask); in GPIO_SecurePrivilegeLock()
208 static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask) in GPIO_EnablePinControlNonSecure() argument
210 base->PCNS |= GPIO_FIT_REG(mask); in GPIO_EnablePinControlNonSecure()
219 static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask) in GPIO_DisablePinControlNonSecure() argument
221 base->PCNS &= GPIO_FIT_REG(~mask); in GPIO_DisablePinControlNonSecure()
230 static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) in GPIO_EnablePinControlNonPrivilege() argument
232 base->PCNP |= GPIO_FIT_REG(mask); in GPIO_EnablePinControlNonPrivilege()
241 static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) in GPIO_DisablePinControlNonPrivilege() argument
243 base->PCNP &= GPIO_FIT_REG(~mask); in GPIO_DisablePinControlNonPrivilege()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DRegLockMacros.h97 #define RLM_REG_BIT_CLEAR8(address, mask) ((*(volatile uint8*)(address))&= (~(mask))) argument
101 #define RLM_REG_BIT_CLEAR16(address, mask) ((*(volatile uint16*)(address))&= (~(mask))) argument
105 #define RLM_REG_BIT_CLEAR32(address, mask) ((*(volatile uint32*)(address))&= (~(mask))) argument
111 #define RLM_REG_BIT_GET8(address, mask) ((*(volatile uint8*)(address))& (mask)) argument
115 #define RLM_REG_BIT_GET16(address, mask) ((*(volatile uint16*)(address))& (mask)) argument
119 #define RLM_REG_BIT_GET32(address, mask) ((*(volatile uint32*)(address))& (mask)) argument
125 #define RLM_REG_BIT_SET8(address, mask) ((*(volatile uint8*)(address))|= (mask)) argument
129 #define RLM_REG_BIT_SET16(address, mask) ((*(volatile uint16*)(address))|= (mask)) argument
133 #define RLM_REG_BIT_SET32(address, mask) ((*(volatile uint32*)(address))|= (mask)) argument
141 #define RLM_REG_RMW8(address, mask, value) (RLM_REG_WRITE8((address), ((RLM_REG_READ8(address)& … argument
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/include/
DRegLockMacros.h97 #define RLM_REG_BIT_CLEAR8(address, mask) ((*(volatile uint8*)(address))&= (~(mask))) argument
101 #define RLM_REG_BIT_CLEAR16(address, mask) ((*(volatile uint16*)(address))&= (~(mask))) argument
105 #define RLM_REG_BIT_CLEAR32(address, mask) ((*(volatile uint32*)(address))&= (~(mask))) argument
111 #define RLM_REG_BIT_GET8(address, mask) ((*(volatile uint8*)(address))& (mask)) argument
115 #define RLM_REG_BIT_GET16(address, mask) ((*(volatile uint16*)(address))& (mask)) argument
119 #define RLM_REG_BIT_GET32(address, mask) ((*(volatile uint32*)(address))& (mask)) argument
125 #define RLM_REG_BIT_SET8(address, mask) ((*(volatile uint8*)(address))|= (mask)) argument
129 #define RLM_REG_BIT_SET16(address, mask) ((*(volatile uint16*)(address))|= (mask)) argument
133 #define RLM_REG_BIT_SET32(address, mask) ((*(volatile uint32*)(address))|= (mask)) argument
141 #define RLM_REG_RMW8(address, mask, value) (RLM_REG_WRITE8((address), ((RLM_REG_READ8(address)& … argument
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/rgpio/
Dfsl_rgpio.h169 static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask) in RGPIO_PortSet() argument
171 base->PSOR = mask; in RGPIO_PortSet()
178 static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask) in RGPIO_SetPinsOutput() argument
180 RGPIO_PortSet(base, mask); in RGPIO_SetPinsOutput()
189 static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask) in RGPIO_PortClear() argument
191 base->PCOR = mask; in RGPIO_PortClear()
201 static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask) in RGPIO_ClearPinsOutput() argument
203 RGPIO_PortClear(base, mask); in RGPIO_ClearPinsOutput()
212 static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask) in RGPIO_PortToggle() argument
214 base->PTOR = mask; in RGPIO_PortToggle()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/igpio/
Dfsl_gpio.h112 static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) in GPIO_PortSet() argument
115 base->DR_SET = mask; in GPIO_PortSet()
117 base->DR |= mask; in GPIO_PortSet()
125 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) in GPIO_SetPinsOutput() argument
127 GPIO_PortSet(base, mask); in GPIO_SetPinsOutput()
136 static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) in GPIO_PortClear() argument
139 base->DR_CLEAR = mask; in GPIO_PortClear()
141 base->DR &= ~mask; in GPIO_PortClear()
149 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) in GPIO_ClearPinsOutput() argument
151 GPIO_PortClear(base, mask); in GPIO_ClearPinsOutput()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/evk-mimxrt1050/
Devkmimxrt1050.c18 .mask = 1 << (0),
23 .mask = 1 << (1),
30 .mask = 1 << (16),
35 .mask = 1 << (17),
42 .mask = 1 << (12),
47 .mask = 1 << (15),
52 .mask = 1 << (14),
57 .mask = 1 << (13),
64 .mask = 1 << (23),
69 .mask = 1 << (22),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/evkb-imxrt1050/
Devkbimxrt1050.c18 .mask = 1 << (0),
23 .mask = 1 << (1),
30 .mask = 1 << (16),
35 .mask = 1 << (17),
42 .mask = 1 << (12),
47 .mask = 1 << (15),
52 .mask = 1 << (14),
57 .mask = 1 << (13),
64 .mask = 1 << (23),
69 .mask = 1 << (22),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/lpcxpresso54114/
Dlpc54114.c19 .mask = 1 << (26),
24 .mask = 1 << (25),
31 .mask = 1 << (20),
36 .mask = 1 << (18),
41 .mask = 1 << (19),
48 .mask = 1 << (8),
53 .mask = 1 << (9),
60 .mask = 1 << (30),
66 .mask = 1 << (8),
71 .mask = 1 << (10),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k22f/
Dfrdm_k22f.c19 .mask = 1 << (2),
26 .mask = 1 << (3),
35 .mask = 1 << (5),
42 .mask = 1 << (6),
49 .mask = 1 << (7),
58 .mask = 1 << (0),
65 .mask = 1 << (1),
74 .mask = 1 << (0),
81 .mask = 1 << (1),
88 .mask = 1 << (1),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-kl27z/
Dfrdm_kl27z.c20 .mask = 1 << (7),
27 .mask = 1 << (6),
36 .mask = 1 << (0),
43 .mask = 1 << (1),
52 .mask = 1 << (5),
59 .mask = 1 << (6),
66 .mask = 1 << (7),
75 .mask = 1 << (1),
82 .mask = 1 << (2),
91 .mask = 1 << (16),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-kl25z/
Dfrdm_kl25z.c20 .mask = 1 << (1),
27 .mask = 1 << (0),
36 .mask = 1 << (1),
43 .mask = 1 << (2),
52 .mask = 1 << (1),
59 .mask = 1 << (2),
66 .mask = 1 << (3),
75 .mask = 1 << (2),
82 .mask = 1 << (1),
91 .mask = 1 << (1),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k64f/
Dfrdm_k64f.c20 .mask = 1 << (24),
27 .mask = 1 << (25),
36 .mask = 1 << (10),
43 .mask = 1 << (11),
52 .mask = 1 << (1),
59 .mask = 1 << (2),
66 .mask = 1 << (3),
75 .mask = 1 << (16),
82 .mask = 1 << (17),
91 .mask = 1 << (2),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k32w042/
Dfrdm_k32w042.c20 .mask = 1 << (10),
27 .mask = 1 << (9),
36 .mask = 1 << (3),
43 .mask = 1 << (2),
52 .mask = 1 << (4),
59 .mask = 1 << (7),
66 .mask = 1 << (5),
75 .mask = 1 << (25),
82 .mask = 1 << (26),
91 .mask = 1 << (11),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-ke15z/
Dfrdm_ke15z.c22 .mask = 1 << (9),
29 .mask = 1 << (8),
38 .mask = 1 << (3),
45 .mask = 1 << (2),
54 .mask = 1 << (0),
61 .mask = 1 << (1),
68 .mask = 1 << (2),
78 .mask = 1 << (8),
85 .mask = 1 << (9),
94 .mask = 1 << (0),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexio/
Dfsl_flexio.h553 static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableShifterStatusInterrupts() argument
555 base->SHIFTSIEN |= mask; in FLEXIO_EnableShifterStatusInterrupts()
566 static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_DisableShifterStatusInterrupts() argument
568 base->SHIFTSIEN &= ~mask; in FLEXIO_DisableShifterStatusInterrupts()
579 static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableShifterErrorInterrupts() argument
581 base->SHIFTEIEN |= mask; in FLEXIO_EnableShifterErrorInterrupts()
592 static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_DisableShifterErrorInterrupts() argument
594 base->SHIFTEIEN &= ~mask; in FLEXIO_DisableShifterErrorInterrupts()
605 static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableTimerStatusInterrupts() argument
607 base->TIMIEN |= mask; in FLEXIO_EnableTimerStatusInterrupts()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/iuart/
Dfsl_uart.c474 void UART_EnableInterrupts(UART_Type *base, uint32_t mask) in UART_EnableInterrupts() argument
476 assert((0x7F3FF73FU & mask) != 0U); in UART_EnableInterrupts()
478 if ((0X3FU & mask) != 0U) in UART_EnableInterrupts()
480 base->UCR1 |= ((mask << UART_UCR1_ADEN_SHIFT) & UART_UCR1_ADEN_MASK) | in UART_EnableInterrupts()
481 (((mask >> 1) << UART_UCR1_TRDYEN_SHIFT) & UART_UCR1_TRDYEN_MASK) | in UART_EnableInterrupts()
482 (((mask >> 2) << UART_UCR1_IDEN_SHIFT) & UART_UCR1_IDEN_MASK) | in UART_EnableInterrupts()
483 (((mask >> 3) << UART_UCR1_RRDYEN_SHIFT) & UART_UCR1_RRDYEN_MASK) | in UART_EnableInterrupts()
484 (((mask >> 4) << UART_UCR1_TXMPTYEN_SHIFT) & UART_UCR1_TXMPTYEN_MASK) | in UART_EnableInterrupts()
485 (((mask >> 5) << UART_UCR1_RTSDEN_SHIFT) & UART_UCR1_RTSDEN_MASK); in UART_EnableInterrupts()
487 if ((0X700U & mask) != 0U) in UART_EnableInterrupts()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/eeprom/
Dfsl_eeprom.h138 static inline void EEPROM_EnableInterrupt(EEPROM_Type *base, uint32_t mask) in EEPROM_EnableInterrupt() argument
140 base->INTENSET = mask; in EEPROM_EnableInterrupt()
150 static inline void EEPROM_DisableInterrupt(EEPROM_Type *base, uint32_t mask) in EEPROM_DisableInterrupt() argument
152 base->INTENCLR = mask; in EEPROM_DisableInterrupt()
175 static inline void EEPROM_ClearInterruptFlag(EEPROM_Type *base, uint32_t mask) in EEPROM_ClearInterruptFlag() argument
177 base->INTSTATCLR = mask; in EEPROM_ClearInterruptFlag()
201 static inline void EEPROM_SetInterruptFlag(EEPROM_Type *base, uint32_t mask) in EEPROM_SetInterruptFlag() argument
203 base->INTSTATSET = mask; in EEPROM_SetInterruptFlag()
266 static inline void EEPROM_SetEccErrorCount(EEPROM_Type *base, uint32_t mask) in EEPROM_SetEccErrorCount() argument
268 base->ECCERRCNT = mask; in EEPROM_SetEccErrorCount()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/rtc/
Dfsl_rtc.c405 void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) in RTC_EnableInterrupts() argument
410 if (0U != ((uint32_t)kRTC_TimeInvalidInterruptEnable & mask)) in RTC_EnableInterrupts()
414 if (0U != ((uint32_t)kRTC_TimeOverflowInterruptEnable & mask)) in RTC_EnableInterrupts()
418 if (0U != ((uint32_t)kRTC_AlarmInterruptEnable & mask)) in RTC_EnableInterrupts()
422 if (0U != ((uint32_t)kRTC_SecondsInterruptEnable & mask)) in RTC_EnableInterrupts()
427 if (0U != ((uint32_t)kRTC_MonotonicOverflowInterruptEnable & mask)) in RTC_EnableInterrupts()
438 if (0U != ((uint32_t)kRTC_TestModeInterruptEnable & mask)) in RTC_EnableInterrupts()
442 if (0U != ((uint32_t)kRTC_FlashSecurityInterruptEnable & mask)) in RTC_EnableInterrupts()
447 if (0U != ((uint32_t)kRTC_TamperPinInterruptEnable & mask)) in RTC_EnableInterrupts()
453 if (0U != ((uint32_t)kRTC_SecurityModuleInterruptEnable & mask)) in RTC_EnableInterrupts()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/lpcxpresso55s16/
Dlpc55s16.c19 .mask = 1 << (21),
25 .mask = 1 << (20),
33 .mask = 1 << (26),
39 .mask = 1 << (3),
45 .mask = 1 << (2),
51 .mask = 1 << (1),
59 .mask = 1 << (29),
65 .mask = 1 << (30),
72 .mask = 1 << (4),
77 .mask = 1 << (7),
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/lpcxpresso55s36/
Dlpc55s36.c18 ….base = GPIO, .pinNumber = 26, .mask = 1 << (26), .clockName = kCLOCK_Gpio1, .portNumber = kGINT_P…
21 ….base = GPIO, .pinNumber = 25, .mask = 1 << (25), .clockName = kCLOCK_Gpio1, .portNumber = kGINT_P…
26 ….base = GPIO, .pinNumber = 24, .mask = 1 << (24), .clockName = kCLOCK_Gpio0, .portNumber = kGINT_P…
29 ….base = GPIO, .pinNumber = 25, .mask = 1 << (25), .clockName = kCLOCK_Gpio0, .portNumber = kGINT_P…
32 ….base = GPIO, .pinNumber = 21, .mask = 1 << (21), .clockName = kCLOCK_Gpio0, .portNumber = kGINT_P…
37 ….base = GPIO, .pinNumber = 29, .mask = 1 << (29), .clockName = kCLOCK_Gpio0, .portNumber = kGINT_P…
40 ….base = GPIO, .pinNumber = 30, .mask = 1 << (30), .clockName = kCLOCK_Gpio0, .portNumber = kGINT_P…
44 ….base = GPIO, .pinNumber = 4, .mask = 1 << (4), .clockName = kCLOCK_Gpio1, .portNumber = kGINT_Por…
46 ….base = GPIO, .pinNumber = 7, .mask = 1 << (7), .clockName = kCLOCK_Gpio1, .portNumber = kGINT_Por…
48 ….base = GPIO, .pinNumber = 6, .mask = 1 << (6), .clockName = kCLOCK_Gpio1, .portNumber = kGINT_Por…
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/lpcxpresso55s69/
Dlpc55s69.c19 .mask = 1 << (21),
25 .mask = 1 << (20),
33 .mask = 1 << (20),
39 .mask = 1 << (19),
45 .mask = 1 << (21),
53 .mask = 1 << (29),
59 .mask = 1 << (30),
66 .mask = 1 << (4),
71 .mask = 1 << (7),
76 .mask = 1 << (6),
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.h1279 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
1289 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
1305 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
1468 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask) in FLEXCAN_ClearStatusFlags() argument
1472 base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1476 base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1480 base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask); in FLEXCAN_ClearStatusFlags()
1482 base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_ClearStatusFlags()
1485 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) in FLEXCAN_ClearStatusFlags() argument
1488 base->ESR1 = mask; in FLEXCAN_ClearStatusFlags()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/enc/
Dfsl_enc.c383 void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) in ENC_ClearStatusFlags() argument
388 if (0U != ((uint32_t)kENC_HOMETransitionFlag & mask)) in ENC_ClearStatusFlags()
392 if (0U != ((uint32_t)kENC_INDEXPulseFlag & mask)) in ENC_ClearStatusFlags()
396 if (0U != ((uint32_t)kENC_WatchdogTimeoutFlag & mask)) in ENC_ClearStatusFlags()
400 if (0U != ((uint32_t)kENC_PositionCompareFlag & mask)) in ENC_ClearStatusFlags()
412 if (0U != ((uint32_t)kENC_SimultBothPhaseChangeFlag & mask)) in ENC_ClearStatusFlags()
417 if (0U != ((uint32_t)kENC_PositionRollOverFlag & mask)) in ENC_ClearStatusFlags()
421 if (0U != ((uint32_t)kENC_PositionRollUnderFlag & mask)) in ENC_ClearStatusFlags()
437 void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) in ENC_EnableInterrupts() argument
442 if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask)) in ENC_EnableInterrupts()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/qtmr_1/
Dfsl_qtmr.c318 void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) in QTMR_EnableInterrupts() argument
324 if ((mask & (uint16_t)kQTMR_CompareInterruptEnable) != 0UL) in QTMR_EnableInterrupts()
329 if ((mask & (uint16_t)kQTMR_OverflowInterruptEnable) != 0UL) in QTMR_EnableInterrupts()
334 if ((mask & (uint16_t)kQTMR_EdgeInterruptEnable) != 0UL) in QTMR_EnableInterrupts()
344 if ((mask & (uint16_t)kQTMR_Compare1InterruptEnable) != 0UL) in QTMR_EnableInterrupts()
349 if ((mask & (uint16_t)kQTMR_Compare2InterruptEnable) != 0UL) in QTMR_EnableInterrupts()
364 void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) in QTMR_DisableInterrupts() argument
370 if ((mask & (uint16_t)kQTMR_CompareInterruptEnable) != 0UL) in QTMR_DisableInterrupts()
375 if ((mask & (uint16_t)kQTMR_OverflowInterruptEnable) != 0UL) in QTMR_DisableInterrupts()
380 if ((mask & (uint16_t)kQTMR_EdgeInterruptEnable) != 0UL) in QTMR_DisableInterrupts()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/qtmr_2/
Dfsl_qtmr.c271 void QTMR_EnableInterrupts(TMR_Type *base, uint32_t mask) in QTMR_EnableInterrupts() argument
277 if (0U != (mask & (uint32_t)kQTMR_CompareInterruptEnable)) in QTMR_EnableInterrupts()
282 if (0U != (mask & (uint32_t)kQTMR_OverflowInterruptEnable)) in QTMR_EnableInterrupts()
287 if (0U != (mask & (uint32_t)kQTMR_EdgeInterruptEnable)) in QTMR_EnableInterrupts()
295 if (0U != (mask & (uint32_t)kQTMR_Compare1InterruptEnable)) in QTMR_EnableInterrupts()
300 if (0U != (mask & (uint32_t)kQTMR_Compare2InterruptEnable)) in QTMR_EnableInterrupts()
314 void QTMR_DisableInterrupts(TMR_Type *base, uint32_t mask) in QTMR_DisableInterrupts() argument
320 if (0U != (mask & (uint32_t)kQTMR_CompareInterruptEnable)) in QTMR_DisableInterrupts()
325 if (0U != (mask & (uint32_t)kQTMR_OverflowInterruptEnable)) in QTMR_DisableInterrupts()
330 if (0U != (mask & (uint32_t)kQTMR_EdgeInterruptEnable)) in QTMR_DisableInterrupts()
[all …]

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