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Searched refs:csr (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/mipi_csi2rx/
Dfsl_mipi_csi2rx.c119 MIPI_CSI_CSR_Type *csr = CSI2RX_GET_CSR(base); in MIPI_CSI2RX_SoftwareReset() local
123 …csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK; in MIPI_CSI2RX_SoftwareReset()
127 …csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK; in MIPI_CSI2RX_SoftwareReset()
128 … csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_SW_RESET_MASK | in MIPI_CSI2RX_SoftwareReset()
135 MIPI_CSI_CSR_Type *csr = CSI2RX_GET_CSR(base); in MIPI_CSI2RX_InitInterface() local
138 csr->PLM_CTRL = 0; in MIPI_CSI2RX_InitInterface()
141 csr->PHY_CTRL = MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK | /* Enable RX. */ in MIPI_CSI2RX_InitInterface()
149 csr->VC_INTERLACED = 0U; in MIPI_CSI2RX_InitInterface()
153 csr->DATA_TYPE_DISABLE_BF = 0U; in MIPI_CSI2RX_InitInterface()
155 csr->DATA_TYPE_DIS = 0U; in MIPI_CSI2RX_InitInterface()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_soc_mipi_dsi.h34 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
36 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
38 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
40 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
70 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_EnableUlps() local
74 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in SOC_MIPI_DSI_EnableUlps()
78 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in SOC_MIPI_DSI_EnableUlps()
90 MIPI_DSI_CSR_Type *csr = SOC_MIPI_DSI_GetCsr(base); in SOC_MIPI_DSI_SetPixelDpiMap() local
92 MIPI_DSI_CSR_PXL2DPI(csr) = pxl2dpi; in SOC_MIPI_DSI_SetPixelDpiMap()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/mipi_dsi_split/
Dfsl_mipi_dsi.c77 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->ULPS_CTRL) argument
79 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CTRL) argument
81 #define MIPI_DSI_CSR_ULPS_CTRL(csr) ((csr)->TX_ULPS_ENABLE) argument
83 #define MIPI_DSI_CSR_PXL2DPI(csr) ((csr)->PXL2DPI_CONFIG) argument
430 MIPI_DSI_CSR_Type *csr = DSI_GET_CSR(base); in DSI_Init() local
433 MIPI_DSI_CSR_ULPS_CTRL(csr) = MIPI_DSI_CSR_ULPS_CTRL_ULPS_MASK; in DSI_Init()
437 MIPI_DSI_CSR_ULPS_CTRL(csr) = 0U; in DSI_Init()
550 MIPI_DSI_CSR_Type *csr = DSI_GET_CSR(base); in DSI_SetDpiConfig() local
551 MIPI_DSI_CSR_PXL2DPI(csr) = (uint32_t)config->dpiColorCoding; in DSI_SetDpiConfig()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/spdif/
Dfsl_spdif_edma.c133 uint16_t csr; in SPDIF_SubmitTransfer() local
179 …csr = (handle->tcdPool[previousTcd].CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MA… in SPDIF_SubmitTransfer()
180 handle->tcdPool[previousTcd].CSR = csr; in SPDIF_SubmitTransfer()
194 csr = (tcdRegs->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; in SPDIF_SubmitTransfer()
196 tcdRegs->CSR = csr; in SPDIF_SubmitTransfer()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/dma3/
Dfsl_edma.c1113 uint16_t csr; in EDMA_SubmitTransfer() local
1159 csr = in EDMA_SubmitTransfer()
1161 handle->tcdPool[previousTcd].CSR = csr; in EDMA_SubmitTransfer()
1179 … csr = (tcdRegs->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
1182 tcdRegs->CSR = csr; in EDMA_SubmitTransfer()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/edma/
Dfsl_edma.c1147 uint16_t csr; in EDMA_SubmitTransfer() local
1193 csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); in EDMA_SubmitTransfer()
1194 csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); in EDMA_SubmitTransfer()
1195 handle->tcdPool[previousTcd].CSR = csr; in EDMA_SubmitTransfer()
1212 csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; in EDMA_SubmitTransfer()
1214 tcdRegs->CSR = csr; in EDMA_SubmitTransfer()