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Searched refs:baseAddr (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c145 #define Qspi_Ip_Sfp_Configure(baseAddr, userConfigPtr) OsIf_Trusted_Call2params(Qspi_Ip_Sfp_Configu… argument
146 …Qspi_Ip_ResetPrivilegedRegisters(baseAddr) OsIf_Trusted_Call1param(Qspi_Ip_ResetPrivilegedRegister… argument
147 …ne Qspi_Ip_Sfp_ClearLatchedErrors(baseAddr) OsIf_Trusted_Call1param(Qspi_Ip_Sfp_ClearLatchedErrors… argument
151 #define Qspi_Ip_Sfp_Configure(baseAddr, userConfigPtr) Qspi_Ip_Sfp_Configure_Privileged(baseAddr, u…
152 #define Qspi_Ip_ResetPrivilegedRegisters(baseAddr) Qspi_Ip_ResetPrivilegedRegisters_Privileged(base…
153 #define Qspi_Ip_Sfp_ClearLatchedErrors(baseAddr) Qspi_Ip_Sfp_ClearLatchedErrors_Privileged(baseAddr)
224 void Qspi_Ip_Sfp_Configure_Privileged(QuadSPI_Type * baseAddr, Qspi_Ip_ControllerConfigType const *…
251 const QuadSPI_Type *baseAddr, in Qspi_Ip_ProcessDataRead() argument
272 recvData = baseAddr->RBDR[cnt]; in Qspi_Ip_ProcessDataRead()
297 …*((uint32 *)((Qspi_Ip_UintPtrType)data)) = baseAddr->RBDR[cnt]; /* Casting through uint32 to avoi… in Qspi_Ip_ProcessDataRead()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
304 … ENDIANNESS((uint32)((((uint32)(regAddr)) - ((uint32)(baseAddr)))>>0x2U)))
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
393 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
394 …(uint8)(SLBR_SET_BIT_8BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SLB…
397 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem)
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
403 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
404 …(uint8)(SLBR_SET_BIT_16BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SL…
407 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem)
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/include/
DRegLockMacros.h303 #define SLBR_ADDR32(baseAddr, regAddr, prot_mem) (((uint32)(baseAddr)) + ((prot_mem) * SLBR_ADDR_O… argument
304 … ENDIANNESS((uint32)((((uint32)(regAddr)) - ((uint32)(baseAddr)))>>0x2U)))
391 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem) \ argument
393 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
394 …(uint8)(SLBR_SET_BIT_8BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SLB…
397 #define REG_SET_SOFT_LOCK8(baseAddr, regAddr, prot_mem)
401 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem) \ argument
403 RLM_REG_WRITE8(SLBR_ADDR32((baseAddr), (regAddr), (prot_mem)), \
404 …(uint8)(SLBR_SET_BIT_16BIT_REG_MASK_U8 >> ((((regAddr) - (baseAddr)) & MODULO_4_BIT_MASK_U32) ^ SL…
407 #define REG_SET_SOFT_LOCK16(baseAddr, regAddr, prot_mem)
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_audiomix.c40 volatile uint32_t *baseAddr = (volatile uint32_t *)((uintptr_t)base + offset); in AUDIOMIX_AttachClk() local
42 *baseAddr = (*baseAddr & ~mask) | value; in AUDIOMIX_AttachClk()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimx8mp/project_template/
Dfsl_audiomix.c40 volatile uint32_t *baseAddr = (volatile uint32_t *)((uint32_t)base + offset); in AUDIOMIX_AttachClk() local
42 *baseAddr = (*baseAddr & ~mask) | value; in AUDIOMIX_AttachClk()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML8/drivers/
Dfsl_audiomix.c40 volatile uint32_t *baseAddr = (volatile uint32_t *)((uintptr_t)base + offset); in AUDIOMIX_AttachClk() local
42 *baseAddr = (*baseAddr & ~mask) | value; in AUDIOMIX_AttachClk()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_audiomix.c40 volatile uint32_t *baseAddr = (volatile uint32_t *)((uintptr_t)base + offset); in AUDIOMIX_AttachClk() local
42 *baseAddr = (*baseAddr & ~mask) | value; in AUDIOMIX_AttachClk()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_audiomix.c40 volatile uint32_t *baseAddr = (volatile uint32_t *)((uintptr_t)base + offset); in AUDIOMIX_AttachClk() local
42 *baseAddr = (*baseAddr & ~mask) | value; in AUDIOMIX_AttachClk()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/nand/flexspi/
Dfsl_flexspi_nand_flash.c30 …atic status_t flexspi_nand_write_enable(FLEXSPI_Type *base, flexspi_port_t port, uint32_t baseAddr) in flexspi_nand_write_enable() argument
36 flashXfer.deviceAddress = baseAddr; in flexspi_nand_write_enable()
48 …lexspi_nand_wait_bus_busy(FLEXSPI_Type *base, flexspi_mem_nand_handle_t *handle, uint32_t baseAddr) in flexspi_nand_wait_bus_busy() argument
56 flashXfer.deviceAddress = baseAddr; in flexspi_nand_wait_bus_busy()
89 uint32_t baseAddr, in flexspi_nand_check_ecc_status() argument
97 flashXfer.deviceAddress = baseAddr; in flexspi_nand_check_ecc_status()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/dpu/
Dfsl_dpu.c966 static bool DPU_CheckBufferAlignment(uint8_t bitsPerPixel, uint32_t baseAddr, uint32_t strideBytes);
1026 static bool DPU_CheckBufferAlignment(uint8_t bitsPerPixel, uint32_t baseAddr, uint32_t strideBytes) in DPU_CheckBufferAlignment() argument
1053 if (0U != ((baseAddr & mask) | (strideBytes & mask))) in DPU_CheckBufferAlignment()
1974 config->baseAddr = 0U; in DPU_CorrdinatesGetDefaultConfig()
1999 if (!DPU_CheckBufferAlignment(config->bitsPerPixel, config->baseAddr, config->strideBytes)) in DPU_InitWarpCoordinates()
2010 fetchEco->LAYER[0].BASEADDRESS = config->baseAddr; in DPU_InitWarpCoordinates()
2055 config->baseAddr = 0U; in DPU_SrcBufferGetDefaultConfig()
2084 if (!(DPU_CheckBufferAlignment(config->bitsPerPixel, config->baseAddr, config->strideBytes))) in DPU_SetFetchUnitSrcBufferConfig()
2091 control->BASEADDRESS = config->baseAddr; in DPU_SetFetchUnitSrcBufferConfig()
2109 …tFetchUnitSrcBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_t baseAddr) in DPU_SetFetchUnitSrcBufferAddr() argument
[all …]
Dfsl_dpu.h451 uint32_t baseAddr; /*!< Source buffer base address. */ member
501 uint32_t baseAddr; /*!< Source buffer base address, see alignment restrictions. */ member
535 …uint32_t baseAddr; /*!< Destination buffer base address, see alignment restrictions. … member
1341 …FetchUnitSrcBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_t baseAddr);
1547 void DPU_SetStoreDstBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t baseAddr);
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_TrustedFunctions.h77 extern void Qspi_Ip_Sfp_Configure_Privileged(QuadSPI_Type * baseAddr,
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1170evkb/
Dmflash_drv.c158 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
164 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1160/
Dmflash_drv.c173 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
179 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt685/
Dmflash_drv.c195 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal) in flexspi_nor_write_enable() argument
201 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1021/
Dmflash_drv.c173 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
179 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1024/
Dmflash_drv.c173 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
179 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1170/
Dmflash_drv.c173 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
179 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt595/
Dmflash_drv.c191 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal) in flexspi_nor_write_enable() argument
197 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt685audevk/
Dmflash_drv.c186 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
192 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/mflash/mimxrt1052/
Dmflash_drv.c181 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
187 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/internal_flash/evkmimxrt1040/
Dfsl_adapter_flexspi_nor_flash.c167 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
173 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/internal_flash/octal_flash/RT595/
Dfsl_adapter_flexspi_nor_flash.c180 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal) in flexspi_nor_write_enable() argument
186 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/internal_flash/octal_flash/
Dfsl_adapter_flexspi_nor_flash.c189 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr, bool enableOctal) in flexspi_nor_write_enable() argument
195 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/internal_flash/evkbmimxrt1060/
Dfsl_adapter_flexspi_nor_flash.c175 static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) in flexspi_nor_write_enable() argument
181 flashXfer.deviceAddress = baseAddr; in flexspi_nor_write_enable()

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