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Searched refs:Value (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h153 boolean Value) in Emios_Pwm_Ip_SetOutputUpdate() argument
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetOutputUpdate()
187 boolean Value) in Emios_Pwm_Ip_SetChannelEnable() argument
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel); in Emios_Pwm_Ip_SetChannelEnable()
213 Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_SetUCRegA() argument
215 Base->CH.UC[Channel].A = eMIOS_A_A(Value); in Emios_Pwm_Ip_SetUCRegA()
239 Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_SetUCRegB() argument
241 Base->CH.UC[Channel].B = eMIOS_B_B(Value); in Emios_Pwm_Ip_SetUCRegB()
280 boolean Value) in Emios_Pwm_Ip_SetFreezeEnable() argument
282 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetFreezeEnable()
[all …]
DEmios_Pwm_Ip.h395 boolean Value);
407 Emios_Pwm_Ip_CounterBusSourceType Value);
419 Emios_Pwm_Ip_InternalClkPsType Value);
459 void Emios_Pwm_Ip_UpdateUCRegA(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
472 void Emios_Pwm_Ip_UpdateUCRegB(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value);
/hal_nxp-3.5.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c387 DmaTcdList[0u].Value = 0u; /* dummy src address read, it will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
388 DmaTcdList[1u].Value = (uint32)&Base->PUSHR.FIFO.CMD; /* dest address write*/ in Spi_Ip_CmdDmaTcdSGInit()
389 DmaTcdList[2u].Value = 0u; /* no src offset */ in Spi_Ip_CmdDmaTcdSGInit()
390 DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
391 DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes dest transfer size */ in Spi_Ip_CmdDmaTcdSGInit()
392 DmaTcdList[5u].Value = 2u; /* bytes to transfer for each request */ in Spi_Ip_CmdDmaTcdSGInit()
393 DmaTcdList[6u].Value = 0u; /* no dest offset */ in Spi_Ip_CmdDmaTcdSGInit()
394 DmaTcdList[7u].Value = 0u; /* dummy iteration count will be updated later */ in Spi_Ip_CmdDmaTcdSGInit()
395 …DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be u… in Spi_Ip_CmdDmaTcdSGInit()
427 DmaTcdList[1u].Value = (uint32)&Base->PUSHR.FIFO.TX; /* dest address write*/ in Spi_Ip_TxDmaTcdSGInit()
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/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer.c240 uint32 Value = 0u; in OsIf_GetCounter() local
243 Value = OsIf_Timer_Dummy_GetCounter(); in OsIf_GetCounter()
247 Value = OsIf_Timer_System_GetCounter(); in OsIf_GetCounter()
252 Value = OsIf_Timer_Custom_GetCounter(); in OsIf_GetCounter()
257 return Value; in OsIf_GetCounter()
264 uint32 Value = 0u; in OsIf_GetElapsed() local
267 Value = OsIf_Timer_Dummy_GetElapsed(CurrentRef); in OsIf_GetElapsed()
271 Value = OsIf_Timer_System_GetElapsed(CurrentRef); in OsIf_GetElapsed()
276 Value = OsIf_Timer_Custom_GetElapsed(CurrentRef); in OsIf_GetElapsed()
281 return Value; in OsIf_GetElapsed()
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/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer.c240 uint32 Value = 0u; in OsIf_GetCounter() local
243 Value = OsIf_Timer_Dummy_GetCounter(); in OsIf_GetCounter()
247 Value = OsIf_Timer_System_GetCounter(); in OsIf_GetCounter()
252 Value = OsIf_Timer_Custom_GetCounter(); in OsIf_GetCounter()
257 return Value; in OsIf_GetCounter()
264 uint32 Value = 0u; in OsIf_GetElapsed() local
267 Value = OsIf_Timer_Dummy_GetElapsed(CurrentRef); in OsIf_GetElapsed()
271 Value = OsIf_Timer_System_GetElapsed(CurrentRef); in OsIf_GetElapsed()
276 Value = OsIf_Timer_Custom_GetElapsed(CurrentRef); in OsIf_GetElapsed()
281 return Value; in OsIf_GetElapsed()
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/hal_nxp-3.5.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h285 uint32 Value = ADC_THRHLR_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
287 AdcBasePtr->THRHLR[RegisterNumber] = Value; in Adc_Sar_WriteThresholds()
291 uint32 Value = ADC_THRHLR0_THRH(HighThreshold) | in Adc_Sar_WriteThresholds() local
296 *THRHLR0Addr = Value; in Adc_Sar_WriteThresholds()
299 *THRHLR1Addr = Value; in Adc_Sar_WriteThresholds()
302 *THRHLR2Addr = Value; in Adc_Sar_WriteThresholds()
305 *THRHLR3Addr = Value; in Adc_Sar_WriteThresholds()
308 *THRHLR4Addr = Value; in Adc_Sar_WriteThresholds()
311 *THRHLR5Addr = Value; in Adc_Sar_WriteThresholds()
315 *THRHLR6Addr = Value; in Adc_Sar_WriteThresholds()
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/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Pll.c187 uint32 Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize() local
196 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
197 Value &= ~(PLL_PLLDV_RDIV_MASK | PLL_PLLDV_MFI_MASK); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
198 Value |= (uint32) (PLL_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
200 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
203 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
204 Value &= ~(PLL_PLLFD_MFN_MASK | PLL_PLLFD_SDMEN_MASK); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
205 Value |= PLL_PLLFD_MFN(Config->NumeratorFracLoopDiv); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
206 Value |= PLL_PLLFD_SDMEN(Config->SigmaDelta); in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
207 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_Divider.c161 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
165 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
196 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
243 if (Config->Value != 0U) in Clock_Ip_SetPllPll0divDeDivOutput()
248 RegValue |= PLL_PLLODIV_DIV(Config->Value - 1U); in Clock_Ip_SetPllPll0divDeDivOutput()
272 DividerValue = (Config->Value != 0U) ? Config->Value : 1U; in Clock_Ip_SetPllPlldvOdiv2Output()
DClock_Ip_Selector.c192 …SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value correspondi… in Clock_Ip_SetCgmXCscCssClkswSwip()
324 …SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value correspondi… in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
496 …SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value correspondi… in Clock_Ip_SetCgmXCscCssCsGrip()
580 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryRtcHardwareValue[Config->Value]; /* Hw value c… in Clock_Ip_SetRtcRtccClksel_TrustedCall()
DClock_Ip.c250 …Ip_SetExternalSignalFrequency((*(Config->ExtClks))[Index].Name, (*(Config->ExtClks))[Index].Value); in Clock_Ip_UpdateDriverContext()
858 if ((PLL_TYPE != Clock_Ip_aeSourceTypeClockName[(*(Config->Selectors))[Index].Value])) in Clock_Ip_InitClock()
973 … if (PLL_TYPE == Clock_Ip_aeSourceTypeClockName[(*(Clock_Ip_pxConfig->Selectors))[Index].Value]) in Clock_Ip_DistributePll()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Pll.c185 uint32 Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize() local
206 Value = (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider) | in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
208 Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
210 Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
211 Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
212 Value |= PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
213 Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta); in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
214 Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
216 Value = (uint32) (PLLDIG_PLLFM_SSCGBYP(Config->FrequencyModulationBypass) | in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
220 Clock_Ip_apxPll[Instance].PllInstance->PLLFM = Value; in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
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DClock_Ip_FracDiv.c150 uint32 IntegerPart = Config->Value[0U]; /* Integer part. */ in Clock_Ip_SetDfsMfiMfn()
151 uint32 FractionalPart = Config->Value[1U]; /* Fractional part. */ in Clock_Ip_SetDfsMfiMfn()
153 uint32 Value = 0U; in Clock_Ip_SetDfsMfiMfn() local
159 Value |= DFS_DVPORT_MFN(FractionalPart); in Clock_Ip_SetDfsMfiMfn()
160 Value |= DFS_DVPORT_MFI(IntegerPart); in Clock_Ip_SetDfsMfiMfn()
161 Clock_Ip_apxDfs[Instance]->DVPORT[DividerIndex] = Value; in Clock_Ip_SetDfsMfiMfn()
DClock_Ip_Divider.c151 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
155 RegValue |= (((Config->Value-1U) << DividerShift) & DividerMask); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
186 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
222 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
226 RegValue |= ((Config->Value-1U) << DividerShift) & DividerMask; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
246 if (Config->Value != 0U) in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
276 if (Config->Value != 0U) in Clock_Ip_SetPlldigPll0divDeDivOutput()
281 RegValue |= PLLDIG_PLLODIV_DIV(Config->Value - 1U); in Clock_Ip_SetPlldigPll0divDeDivOutput()
DClock_Ip_Selector.c167 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetCgmXCscCssClkswSwip()
285 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryHardwareValue[Config->Value]; /* Hw value corr… in Clock_Ip_SetCgmXCscCssCsGrip()
352 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryClkoutHardwareValue[Config->Value]; /* Hw valu… in Clock_Ip_SetGprXClkoutSelMuxsel()
378 …uint32 SelectorValue = Clock_Ip_au16SelectorEntryAeHardwareValue[Config->Value]; /* Hw value co… in Clock_Ip_SetMcMeAeGssSysclk_TrustedCall()
DClock_Ip.c245 … Clock_Ip_SetExternalSignalFrequency(Config->ExtClks[Index].Name, Config->ExtClks[Index].Value); in Clock_Ip_UpdateDriverContext()
839 if ((PLL_TYPE != Clock_Ip_aeSourceTypeClockName[Config->Selectors[Index].Value])) in Clock_Ip_InitClock()
954 … if (PLL_TYPE == Clock_Ip_aeSourceTypeClockName[Clock_Ip_pxConfig->Selectors[Index].Value]) in Clock_Ip_DistributePll()
/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c1711 DmaTransferList[0].Value = (uint32)TxBuff; in Linflexd_Uart_Ip_StartSendUsingDma()
1713 DmaTransferList[1].Value = LINFLEXD_UART_IP_LSBW_ADDR(Base->BDRL); in Linflexd_Uart_Ip_StartSendUsingDma()
1716 DmaTransferList[3].Value = 0; in Linflexd_Uart_Ip_StartSendUsingDma()
1723 DmaTransferList[2].Value = 1; in Linflexd_Uart_Ip_StartSendUsingDma()
1724 DmaTransferList[4].Value = TxSize; in Linflexd_Uart_Ip_StartSendUsingDma()
1725 DmaTransferList[5].Value = 1; in Linflexd_Uart_Ip_StartSendUsingDma()
1726 DmaTransferList[6].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; in Linflexd_Uart_Ip_StartSendUsingDma()
1727 DmaTransferList[7].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; in Linflexd_Uart_Ip_StartSendUsingDma()
1731 DmaTransferList[2].Value = 2; in Linflexd_Uart_Ip_StartSendUsingDma()
1732 DmaTransferList[4].Value = TxSize/(uint32)2; in Linflexd_Uart_Ip_StartSendUsingDma()
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c937 global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel); in Emios_Icu_Ip_StartTimestamp()
941 global_DmaChannelTransferList[1U].Value = (uint32)bufferPtr; in Emios_Icu_Ip_StartTimestamp()
943 global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
945 global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE; in Emios_Icu_Ip_StartTimestamp()
947 global_DmaChannelTransferList[4U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
949 global_DmaChannelTransferList[5U].Value = (uint32)4U; in Emios_Icu_Ip_StartTimestamp()
951 global_DmaChannelTransferList[6U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
953 global_DmaChannelTransferList[7U].Value = (uint32)0U; in Emios_Icu_Ip_StartTimestamp()
958 global_DmaChannelTransferList[8U].Value = 4U; in Emios_Icu_Ip_StartTimestamp()
960 global_DmaChannelTransferList[9U].Value = bufferSize; in Emios_Icu_Ip_StartTimestamp()
[all …]
DEmios_Icu_Ip_Irq.c1179 …Dma_IpChUpdateDestAddress[0U].Value = (uint32)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[ins… in Emios_Icu_Ip_TimestampDmaProcessing()
1187 …Dma_IpChUpdateIterCount[0U].Value = (uint32)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[insta… in Emios_Icu_Ip_TimestampDmaProcessing()
1189 Dma_IpChUpdateIterCount[1U].Value = (uint32)0U; in Emios_Icu_Ip_TimestampDmaProcessing()
1203 …Dma_IpChUpdateIterCount[0U].Value = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwC… in Emios_Icu_Ip_TimestampDmaProcessing()
1209 Dma_IpChUpdateIterCount[0U].Value = noOfBufferElemToFill; in Emios_Icu_Ip_TimestampDmaProcessing()
1238 …Dma_IpChUpdateDestAddress[0U].Value = (uint32)&Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState… in Emios_Icu_Ip_SignalMeasurementDmaProcessing()
1271 …Dma_IpChUpdateDestAddress[0U].Value = (uint32)&Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState… in Emios_Icu_Ip_SignalMeasurementDmaProcessing()
1274 Dma_IpChUpdateIterCount[0U].Value = (uint16)EMIOS_ICU_IP_DMA_MAJORLOOP_COUNT; in Emios_Icu_Ip_SignalMeasurementDmaProcessing()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/src/
DEmios_Mcl_Ip.c472 void Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance, uint8 Value) in Emios_Mcl_Ip_ConfigureGlobalTimebase() argument
476 DevAssert(((uint8)STD_ON == Value)||((uint8)STD_OFF == Value)); in Emios_Mcl_Ip_ConfigureGlobalTimebase()
481 if ((uint8)STD_ON == Value) in Emios_Mcl_Ip_ConfigureGlobalTimebase()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/include/
DEmios_Mcl_Ip.h257 void Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance, uint8 Value);
/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c2752 boolean Value) in Emios_Pwm_Ip_SetPreEnableClock() argument
2762 Emios_Pwm_Ip_SetPrescalerEnable(Base, Channel, Value); in Emios_Pwm_Ip_SetPreEnableClock()
2774 Emios_Pwm_Ip_CounterBusSourceType Value) in Emios_Pwm_Ip_SetBusSelected() argument
2783 Emios_Pwm_Ip_SetCounterBus(Base, Channel, Value); in Emios_Pwm_Ip_SetBusSelected()
2795 Emios_Pwm_Ip_InternalClkPsType Value) in Emios_Pwm_Ip_SetClockPs() argument
2806 Emios_Pwm_Ip_SetExtendedPrescaler(Base, Channel, Value); in Emios_Pwm_Ip_SetClockPs()
2923 void Emios_Pwm_Ip_UpdateUCRegA(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_UpdateUCRegA() argument
2931 Emios_Pwm_Ip_SetUCRegA(Base, Channel, Value); in Emios_Pwm_Ip_UpdateUCRegA()
2944 void Emios_Pwm_Ip_UpdateUCRegB(uint8 Instance, uint8 Channel, Emios_Pwm_Ip_PeriodType Value) in Emios_Pwm_Ip_UpdateUCRegB() argument
2952 Emios_Pwm_Ip_SetUCRegB(Base, Channel, Value); in Emios_Pwm_Ip_UpdateUCRegB()
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Types.h2997 …Clock_Ip_NameType Value; /**< Name of the selected input so… member
3008 …uint32 Value; /**< Divider value - if value is zero th… member
3034 uint32 Value[2U]; /**< Fractional dividers */ member
3045 …uint32 Value; /**< Enable value - if value is zero the… member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Types.h2847 …Clock_Ip_NameType Value; /**< Name of the selected input so… member
2858 …uint32 Value; /**< Divider value - if value is zero th… member
2884 uint32 Value[2U]; /**< Fractional dividers */ member
2895 …uint32 Value; /**< Enable value - if value is zero the… member