1.. zephyr:board:: warp7
2
3Overview
4********
5
6The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7
7core and Single Cortex M4 core.
8Zephyr was ported to run on the M4 core. In a later release, it will also
9communicate with the A7 core (running Linux) via RPmsg.
10
11Hardware
12********
13
14The WaRP7 Platform is composed of a CPU and IO board.
15
16WaRP7 IO Board
17==============
18
19- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface)
20- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface)
21- Altimeter: NXP MPL3115A2 (I2C4 interface)
22- NXP NTAG NT3H1101 (I2C2 interface)
23- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces)
24- S1 - Reset Button (POR_B signal)
25- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal)
26- S3 - On/Off (MX7_ONOFF signal)
27- Board to board connector (34 configurable pins)
28- mikroBUS expansion connector
29- 10-pin needle JTAG Connector
30- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4)
31- MIPI DSI 1 lane Connector
32- LCD Touch Connector (I2C2 interface)
33- Audio Jack: Mic and Stereo Headphone
34
35WaRP7 CPU Board
36===============
37
38- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and
39  Single Cortex M4 (200MHz) core
40- Memory
41
42  - RAM -> A7: 4GB (Kingston 08EMCP04)
43  - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
44  - Flash -> A7: 8GB eMMC (Kingston 08EMCP04)
45- Multimedia
46
47  - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface)
48- Connectivity
49
50  - Board to board connector (34 configurable pins)
51  - Micro USB 2.0 OTG connector (USB_OTG1 interface)
52  - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR
53    (SD1, UART3 SAI2 interfaces)
54- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface)
55- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface)
56
57
58For more information about the i.MX7 SoC and WaRP7, see these references:
59
60- `i.MX 7 Series Website`_
61- `i.MX 7 Solo Datasheet`_
62- `i.MX 7 Solo Reference Manual`_
63- `WaRP7 Site`_
64- `WaRP7 Quick Start Guide`_
65- `WaRP7 User Guide`_
66- `WaRP7 GitHub repository`_
67
68Supported Features
69==================
70
71.. zephyr:board-supported-hw::
72
73Connections and IOs
74===================
75
76The WaRP7 board Board was tested with the following pinmux controller
77configuration.
78
79+---------------+---------------------+--------------------------------+
80| Board Name    | SoC Name            | Usage                          |
81+===============+=====================+================================+
82| FT_TX2        | UART2_TXD           | UART Console                   |
83+---------------+---------------------+--------------------------------+
84| FT_RX2        | UART2_RXD           | UART Console                   |
85+---------------+---------------------+--------------------------------+
86| MKBUS_TX      | UART6_TXD           | UART                           |
87+---------------+---------------------+--------------------------------+
88| MKBUS_RX      | UART6_RXD           | UART                           |
89+---------------+---------------------+--------------------------------+
90| S2            | ENET1_RD1/GPIO7_IO1 | SW0                            |
91+---------------+---------------------+--------------------------------+
92| I2C4_SDA      | I2C4_SDA            | I2C / FXOS8700 / FXAS21002     |
93+---------------+---------------------+--------------------------------+
94| I2C4_SCL      | I2C4_SCL            | I2C / FXOS8700 / FXAS21002     |
95+---------------+---------------------+--------------------------------+
96| SENSOR_INT_B  | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 |
97+---------------+---------------------+--------------------------------+
98
99System Clock
100============
101
102The M4 Core is configured to run at a 200 MHz clock speed.
103
104Serial Port
105===========
106
107The iMX7S SoC has seven UARTs. The number 2 is configured for the console and
108the number 6 is used in the mikroBUS connector.
109
110Programming and Debugging
111*************************
112
113The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by
114the A7 core. The A7 core is responsible to load the M4 binary application into
115the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and
116get the M4 out of reset.
117The A7 can perform these steps at bootloader level or after the Linux system
118has booted.
119
120The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and
121M4:
122
123+------------+-----------------------+------------------------+-----------------------+----------------------+
124| Region     | Cortex-A7             | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus)  | Size                 |
125+============+=======================+========================+=======================+======================+
126| DDR        | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF  | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) |
127+------------+-----------------------+------------------------+-----------------------+----------------------+
128| OCRAM      | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF  | 0x00900000-0x0091FFFF | 128KB                |
129+------------+-----------------------+------------------------+-----------------------+----------------------+
130| TCMU       | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF  |                       | 32KB                 |
131+------------+-----------------------+------------------------+-----------------------+----------------------+
132| TCML       | 0x007F8000-0x007FFFFF |                        | 0x1FFF8000-0x1FFFFFFF | 32KB                 |
133+------------+-----------------------+------------------------+-----------------------+----------------------+
134| OCRAM_S    | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF  | 0x00000000-0x00007FFF | 32KB                 |
135+------------+-----------------------+------------------------+-----------------------+----------------------+
136| QSPI Flash |                       |                        | 0x08000000-0x0BFFFFFF | 64MB                 |
137+------------+-----------------------+------------------------+-----------------------+----------------------+
138
139
140References
141==========
142
143- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3)
144- `Toradex Wiki`_
145
146
147At compilation time you have to choose which RAM will be used. This
148configuration is done in the file :zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4.dts` with
149"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available
150configurations are:
151
152.. code-block:: none
153
154   "zephyr,flash"
155   - &ddr_code
156   - &tcml_code
157   - &ocram_code
158   - &ocram_s_code
159   - &ocram_pxp_code
160   - &ocram_epdc_code
161
162   "zephyr,sram"
163   - &ddr_sys
164   - &tcmu_sys
165   - &ocram_sys
166   - &ocram_s_sys
167   - &ocram_pxp_sys
168   - &ocram_epdc_sys
169
170
171Below you will find the instructions to load and run Zephyr on M4 from A7 using
172u-boot.
173
174Connect both micro USB interfaces into the PC. In one USB interface you will
175have 2 USB serial ports, the first one is the A7 console and the second is the
176M4 console for Zephyr with both configured to work at 115200 8N1.
177The other USB interface is used to power the CPU and IO boards and is connected
178to the USB OTG interface of the i.MX7S.
179
180After powering up the platform stop the u-boot execution on the A7 core and
181expose the eMMC as mass storage with the following command in the u-boot
182prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT
183partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the
184u-boot prompt.
185Set the u-boot environment variables and run the zephyr.bin from the
186appropriated memory configured in the Zephyr compilation:
187
188.. code-block:: console
189
190   setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr'
191   # TCML
192   setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000'
193   setenv bootm4tcml 'run m4tcml && run bootm4'
194   run bootm4tcml
195   # TCMU
196   setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000'
197   setenv bootm4tcmu 'run m4tcmu && run bootm4'
198   run bootm4tcmu
199   # OCRAM
200   setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000'
201   setenv bootm4ocram 'run m4ocram && run bootm4'
202   run bootm4ocram
203   # OCRAM_S
204   setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000'
205   setenv bootm4ocrams 'run m4ocrams && run bootm4'
206   run bootm4ocrams
207   # DDR
208   setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000'
209   setenv bootm4ddr 'run m4ddr && run bootm4'
210   run bootm4ddr
211
212
213Debugging
214=========
215
216Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
217
218To run Zephyr Binary using J-Link, create the following script to get the
219Program Counter and Stack Pointer from ``zephyr.bin``.
220
221get-pc-sp.sh:
222.. code-block:: console
223
224   #!/bin/sh
225
226   firmware=$1
227
228   pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
229   sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
230
231   echo pc=$pc
232   echo sp=$sp
233
234
235Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
236.. code-block:: console
237
238   pc=00900f01
239   sp=00905020
240
241Plug in the J-Link into the board and PC and run the J-Link command line tool:
242
243.. code-block:: console
244
245   /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \
246      -speed 4000 -autoconnect 1 -jtagconf -1,-1 \
247      -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
248
249The following steps are necessary to run the zephyr.bin:
250
2511. Put the M4 core in reset
2522. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
2533. Set PC (Program Counter)
2544. Set SP (Stack Pointer)
2555. Get the M4 core out of reset
256
257Issue the following commands inside J-Link commander:
258
259.. code-block:: console
260
261   w4 0x3039000C 0xAC
262   loadfile zephyr.bin,0x00900000
263   w4 0x00180000 00900f01
264   w4 0x00180004 00905020
265   w4 0x3039000C 0xAA
266
267With these mechanisms, applications for the ``warp7`` board
268configuration can be built and debugged in the usual way (see
269:ref:`build_an_application` and :ref:`application_run` for more details).
270
271References
272==========
273
274- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_
275- `J-Link iMX7D Instructions`_
276
277.. _WaRP7 Site:
278   https://www.element14.com/warp7
279
280.. _WaRP7 User Guide:
281   https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf
282
283.. _WaRP7 Quick Start Guide:
284   https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf
285
286.. _WaRP7 GitHub repository:
287   https://github.com/WaRP7
288
289.. _i.MX 7 Series Website:
290   https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1
291
292.. _i.MX 7 Solo Datasheet:
293   https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf
294
295.. _i.MX 7 Solo Reference Manual:
296   https://www.nxp.com/webapp/Download?colCode=IMX7SRM
297
298.. _J-Link Tools:
299   https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack
300
301.. _NXP iMX7D Connect CortexM4.JLinkScript:
302   https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript
303
304.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors:
305   https://www.nxp.com/docs/en/application-note/AN5317.pdf
306
307.. _J-Link iMX7D Instructions:
308   https://wiki.segger.com/IMX7D
309
310.. _Toradex Wiki:
311   https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas
312