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Searched refs:USART0 (Results 1 – 25 of 44) sorted by relevance

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/Zephyr-latest/drivers/spi/
Dspi_gecko_usart.c45 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
48 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
52 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
57 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
63 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
70 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
/Zephyr-latest/drivers/serial/
Duart_gecko.c39 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
42 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
46 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
51 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
57 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
64 #define CLOCK_USART(ref) (((ref) == USART0) ? cmuClock_USART0 \
/Zephyr-latest/boards/gd/gd32e507v_start/doc/
Dindex.rst66 is USART0 with TX connected at PB6 and RX at PB7. USART0 is exposed as a
/Zephyr-latest/boards/gd/gd32vf103v_eval/doc/
Dindex.rst71 is USART0 with TX connected at PA9 and RX at PA10.
80 - JP5/6: Select 1-2 positions (labeled as ``USART0``)
/Zephyr-latest/boards/seagate/faze/doc/
Dindex.rst86 | PIO0_18 | UART | USART0 RX |
88 | PIO0_19 | UART | USART0 TX |
/Zephyr-latest/boards/gd/gd32f450z_eval/doc/
Dindex.rst84 is USART0 with TX connected at PA9 and RX at PA10.
93 - JP13: Select 1-2 position (labeled as ``USART0``)
/Zephyr-latest/boards/gd/gd32f470i_eval/doc/
Dindex.rst88 is USART0 with TX connected at PA9 and RX at PA10.
97 - J5: Select 1-2 position (labeled as ``USART0``)
/Zephyr-latest/boards/seagate/legend/doc/
Dindex.rst91 | PA10 | UART | USART0 RX |
93 | PA9 | UART | USART0 TX |
/Zephyr-latest/boards/gd/gd32f450i_eval/doc/
Dindex.rst89 is USART0 with TX connected at PA9 and RX at PA10.
98 - J5: Select 1-2 position (labeled as ``USART0``)
/Zephyr-latest/boards/gd/gd32e507z_eval/doc/
Dindex.rst74 is USART0 with TX connected at PA9 and RX at PA10. USART0 is exposed as a
/Zephyr-latest/boards/gd/gd32f403z_eval/doc/
Dindex.rst78 The default serial port is USART0. This port uses header JP-5/6 to route
94 | 1-2 | 1-2 | USART0 / J2 |
/Zephyr-latest/boards/gd/gd32e103v_eval/doc/
Dindex.rst75 The default serial port is USART0. This port uses header JP-5/6 to route
91 | 1-2 | 1-2 | USART0 / J2 |
/Zephyr-latest/dts/arm/silabs/
Defm32_pg_1b.dtsi43 usart0: usart@40010000 { /* USART0 */
Defm32hg.dtsi43 usart0: usart@4000c000 { /* USART0 */
Defr32fg1p.dtsi44 usart0: usart@40010000 { /* USART0 */
Defr32xg13p.dtsi47 usart0: usart@40010000 { /* USART0 */
Defm32wg.dtsi43 usart0: usart@4000c000 { /* USART0 */
/Zephyr-latest/boards/sipeed/longan_nano/doc/
Dindex.rst79 USART0 is on the opposite end of the USB.
/Zephyr-latest/boards/gd/gd32vf103c_starter/doc/
Dindex.rst70 - JP5/6: Select 1-2 positions (labeled as ``USART0``)
/Zephyr-latest/boards/silabs/radio_boards/slwrb4161a/doc/
Dindex.rst105 USART0 is connected to the board controller and is used for the console.
/Zephyr-latest/boards/silabs/radio_boards/slwrb4170a/doc/
Dindex.rst105 USART0 is connected to the board controller and is used for the console.
/Zephyr-latest/boards/gd/gd32f350r_eval/doc/
Dindex.rst66 is USART0 with TX connected at PA9 and RX at PA10.
/Zephyr-latest/boards/gd/gd32f450v_start/doc/
Dindex.rst66 provides default configuration for USART0 with TX connected at PB6 and RX at
/Zephyr-latest/boards/silabs/dev_kits/sltb009a/doc/
Dindex.rst97 USART0 is connected to the board controller and is used for the console.
/Zephyr-latest/boards/silabs/radio_boards/slwrb4180a/doc/
Dindex.rst104 USART0 is connected to the board controller and is used for the console.

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