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Searched refs:SRX1PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR4_PCTL.h83 __IO uint32_t SRX1PCTL; /**< SRX_1 Clock Control Enable, offset: 0x28 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3956 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR4_PCTL->SRX1PCTL & GPR4_PCTL_SRX1PCTL_PCTL_MASK) >> GP… in Clock_Ip_Get_SRX1_CLK_Frequency()