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Searched refs:SIUL2_MSCR_OBE_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_nxp-3.5.0/s32/soc/s32z27/include/
DSiul2_Port_Ip_Defines.h133 #ifdef SIUL2_MSCR_OBE_MASK
134 #undef SIUL2_MSCR_OBE_MASK
138 #define SIUL2_MSCR_OBE_MASK (0x200000U) macro
141 … (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/Port/src/
DSiul2_Port_Ip.c565 u32TempVal = (u32RegVal & SIUL2_MSCR_OBE_MASK) >> SIUL2_MSCR_OBE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
730 base->MSCR[pin] &= ~SIUL2_MSCR_OBE_MASK; in Siul2_Port_Ip_SetOutputBuffer()
825 base->MSCR[pin] &= ~SIUL2_MSCR_OBE_MASK; in Siul2_Port_Ip_SetPinDirection()
835 base->MSCR[pin] |= (SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_OBE_MASK); in Siul2_Port_Ip_SetPinDirection()
839 base->MSCR[pin] &= ~(SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_OBE_MASK); in Siul2_Port_Ip_SetPinDirection()
/hal_nxp-3.5.0/s32/drivers/s32ze/Port/src/
DSiul2_Port_Ip.c808 u32TempVal = (u32RegVal & SIUL2_MSCR_OBE_MASK) >> SIUL2_MSCR_OBE_SHIFT; in Siul2_Port_Ip_GetMSCRConfiguration()
967 base->MSCR[pin] &= ~SIUL2_MSCR_OBE_MASK; in Siul2_Port_Ip_SetOutputBuffer()
1116 base->MSCR[pin] &= ~SIUL2_MSCR_OBE_MASK; in Siul2_Port_Ip_SetPinDirection()
1136 base->MSCR[pin] |= (SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_OBE_MASK); in Siul2_Port_Ip_SetPinDirection()
1140 base->MSCR[pin] &= ~(SIUL2_MSCR_IBE_MASK | SIUL2_MSCR_OBE_MASK); in Siul2_Port_Ip_SetPinDirection()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SIUL2.h1386 #define SIUL2_MSCR_OBE_MASK (0x200000U) macro
1389 … (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SIUL2.h1776 #define SIUL2_MSCR_OBE_MASK (0x200000U) macro
1779 … (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK)