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Searched refs:SIUL1PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR1_PCTL.h87 …__IO uint32_t SIUL1PCTL; /**< SIUL2_1 Clock Control Enable, offset: 0x38 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3883 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR1_PCTL->SIUL1PCTL & GPR1_PCTL_SIUL1PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SIUL2_1_CLK_Frequency()