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Searched refs:SIUL0PCTL (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR0_PCTL.h90 …__IO uint32_t SIUL0PCTL; /**< SIUL2_0 Clock Control Enable, offset: 0x54 */ member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3874 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->SIUL0PCTL & GPR0_PCTL_SIUL0PCTL_PCTL_MASK) >> … in Clock_Ip_Get_SIUL2_0_CLK_Frequency()