Home
last modified time | relevance | path

Searched refs:PLL_PLLODIV_DE_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_PLL.h216 #define PLL_PLLODIV_DE_MASK (0x80000000U) macro
219 … (((uint32_t)(((uint32_t)(x)) << PLL_PLLODIV_DE_SHIFT)) & PLL_PLLODIV_DE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c241 …_DEV_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLL_PLLODIV_DE_MASK)); in Clock_Ip_SetPllPll0divDeDivOutput()
246 RegValue |= PLL_PLLODIV_DE_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()
DClock_Ip_Pll.c173 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
310 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLL_PLLODIV_DE_MASK; in Clock_Ip_ResetPllRdivMfiMfnOdiv2Sdmen()
DClock_Ip_Frequency.c1850 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI0_Frequency()
1857 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI1_Frequency()
1865 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI0_Frequency()
1874 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI1_Frequency()
1883 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI2_Frequency()